IIEST, Shibpur

Indian Institute of Engineering Science and Technology, Shibpur

(Formerly Bengal Engineering and Science University, Shibpur)

Empowering the nation since 1856

Dr. Surajeet Ghosh

Assistant Professor

Department of Computer Science & Technology

Academic Qualifications

  • Ph.D. (Engineering), Jadavpur University, Kolkata, India
  • M.E. (Computer Science and Engineering), Maulana Abul Kalam Azad University of Technology, (Formerly West Bengal University of Technology), Kolkata, India
  • B.Tech. (Computer Science and Technology), University of Kalyani, Kalyani, West Benagal, India



  1. Mobile: :+91 - 33 - 26686151 / 4561, Extn. - 576


  1. Office address:

    Department of Computer Science & Technology,
    Indian Institute of Engineering Science & Technology,
    (Formerly Bengal Engineering and Science University),
    Shibpur, P.O. - Botanical Garden, Howrah - 711 103, India

  2. Email: surajeet@cs.iiests.ac.inghoshsurajeet@yahoo.com

Area of Research

  • Custom Computing
  • Computational Architecture for Next Generation Sequencing
  • Hardware Architecture for Network Routing Schemes

Courses Undertaken

  • Embedded Systems
  • Computer Organization and Architecture
  • Peripheral Devices and Interfaces
  • Introduction to Computing

Recent Publications (Last 10)

  1. S. S. Ray, N. Srivastava and S. Ghosh, “A hardware-based high-throughput DNA sequence alignment scheme,” 2016 IEEE Annual India Conference (INDICON), Bangalore, India, 2016, pp. 1-6. doi:10.1109/INDICON.2016.7838990

  2.   S. S. Ray, A. Banerjee, A. Datta and S. Ghosh, “A memory efficient DNA sequence alignment technique using pointing matrix,” 2016 IEEE Region 10 Conference(TENCON), Singapore, 2016, pp. 3559-3562. doi:10.1109/TENCON.2016.7848720

  3. S. Ghosh and M. Baliyan, “A hash based architecture of longest prefix matching for fast IP processing,” 2016 IEEE Region 10 Conference (TENCON), Singapore, 2016, pp. 228-231. doi:10.1109/TENCON.2016.7847995

  4.   S. Saha Ray, S. Ghosh, and B. Sardar, “An SRAM-based novel hardware architecture for longest prefix matching for IP route lookup”, Photonic Network Communication,Springer-Verlag New York, Inc., Vol. 32, No. 3 (December 2016), pp. 359-371. doi:10.1007/s11107-016-0674-8

  5.   S. Ray, K. Das and S. Ghosh, “A RAM-Based MAC Table with Two-Tier Security at Layer 2”, IETE Journal of Research, Taylor &Francis, (On line publication Dec. 2015), Vol. 62, No. 4, pp. 435-445, 2016. doi:10.1080/03772063.2015.1117953

  6.   S. S. Ray, S. Ghosh and B. Sardar, “SRAM based longest prefix matching approach for multigigabit IP processing,” 2015 IEEE International Conference on AdvancedNetworks and Telecommuncations Systems (ANTS), Kolkata, 2015, pp. 1-6. doi:10.1109/ANTS.2015.7413624

  7.   S. Ghosh, S. Mandal and S. Saha Ray, “A scalable high-throughput pipeline architecture for DNA sequence alignment,” TENCON 2015 - 2015 IEEE Region 10 Conference, 2015, pp. 1-6.

  8.   S. Ray, A. Bhattacharya and S. Ghosh, “A fast range matching architecture with unit storage expansion ratio and high memory utilization using SBiCAM for packet classification,” 2014 Annual IEEE India Conference (INDICON), 2014, pp. 1-6. doi:10.1109/INDICON.2014.7030357

  9.   S. S. Ray, S. Ghosh and R. Prasad, “Low-cost hierarchical memory-based pipelined architecture for DNA sequence matching,” 2014 Annual IEEE India Conference(INDICON),  2014, pp. 1-6. doi:10.1109/INDICON.2014.7030681

  10.  S. S. Ray, A. Chatterjee and S. Ghosh, “A novel approach for prefix minimization using Ternary Trie (PMTT) for packet classification,” TENCON 2014 - 2014 IEEE Region 10 Conference,  2014, pp. 1-6. doi:10.1109/TENCON.2014.7022466