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Ayan Banerjee

About


Industry Experience: 

From 03/03/1999 to 31/07/2000 at

Centre for Development of Telematics (CDOT), New DelhiCentre for Development of Telematics (CDOT), New Delhi

Academic Qualifications


  • PhD: Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur.
  • M.Tech: 1999 in Electronics and Electrical Communication Engineering with specialization in Integrated Circuits and Systems Engineering from IIT Kharagpur
  • B.E.: 1994 in Electronics and Telecommunication Engineering from Bengal Engineering College, Shibpur, Calcutta University

Research Statement


  • VLSI Architectures for Communication and Biomedical Engineering
  • VLSI Architectures for Deep Learning based Signal Processing Systems
  • CORDIC based DSP Architectures
  • Digital Signal Processing
  • Digital Image Processing

Latest Publications


  • 1 Sayantan Dutta and Ayan Banerjee, Low Latency and Area Efficient Very Large Scale Integration Architecture of 2-Dimensional Bicubic Interpolation using Carry Save Adder Based Fast Multiplier, 686-692, 2020 Fourth International Conference on Inventive Systems and Control (ICISC), 2020
  • 2 Sayantan Dutta and Ayan Banerjee, Low Latency and Area Efficient VLSI Architecture of 2D Bilinear Interpolation using Brent Kung Adder Based Fast Multiplier., 273-278, 2020 Fourth International Conference on Inventive Systems and Control (ICISC), 2020
  • 3 Sayantan Dutta and Ayan Banerjee, Optimal Image Fusion Algorithm using Modified Grey Wolf Optimization amalgamed with Cuckoo Search, Levy Fly and Mantegna Algorithm, 284-290, 2020 2nd International Conference on Innovative Mechanisms for Industry Applications (ICIMIA), 2020
  • 4 Sayantan Dutta and Ayan Banerjee, Optimal Image Fusion Algorithm using Modified Whale Optimization Algorithm Amalgamed with Local Search and BAT Algorithm, 709-715, 2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC), 2020
  • 5 Ayan Banerjee and Anindya Sundar Dhar, A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation., 1-24, Circuits, Systems and Signal Processing, 2020
  • 6 Anirban Chakraborty and Ayan Banerjee, An Adaptive and Automated Image Fusion Algorithm Based on DWT for Real Time Applications, 4th IEEE International Conference on Information Systems and Computer Networks (ISCON 2019), 2019
  • 7 Anirban Ganguly and Ayan Banerjee, Analog VLSI Design of Current Mode DCT for 1D Signal Processing, 4th IEEE International Conference on Information Systems and Computer Networks (ISCON 2019), 2019
  • 8 Debanjana Datta, A. Chaudhuri, Mousumi Bhanja, Baidyanath Ray and Ayan Banerjee, Series Realization of Non-Linear Analog Functions using Current Mode Device, 4th IEEE International Conference on Information Systems and Computer Networks (ISCON 2019), 2019
  • 9 Debanjana Dutta, Mousumi Bhanja, A. Prasad, Baidyanath Ray and Ayan Banerjee, Design of Current-mode High Frequency linear Analog Circuit, IEEE TENSYMP: The IEEE Region 10 Symposium, 2019
  • 10 Debanjana Dutta, S. Agarwal, V. Kumar, M. Raj, Baidyanath Ray and Ayan Banerjee, Design of Current Mode Sigmoid Function and Hyperbolic Tangent Function, 23rd International Symposium on VLSI Design and Test (VDAT-2019), 2019
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    Research Areas


    • VLSI Architecture Design of Deep Learning Based Signal Processing Syatems
    • VLSI Architecture Design of Image Processing Methods
    • CORDIC based DSP architectures
    • VLSI Architectures for Communication and Biomedical Engineering

    Publications


    1 Ayan Banerjee and Anindya Sundar Dhar, A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation., 1-24, Circuits, Systems and Signal Processing, 2020
  • 2 Anirban Chakraborty and Ayan Banerjee, Area and Memory Efficient Tunable VLSI implementation Of DWT Filters for Image Decomposition Using DA, International Journal of Electronics, Taylor and Francis, 2019
  • 3 Anirban Chakraborty and Ayan Banerjee, A Memory Efficient, Multiplierless and Modular VLSI Architecture of 1D/2D Re-configurable 9/7 and 5/3 DWT Filters Using Distributed Arithmetic, Journal of Circuits, Systems and Computers, World Scientific, 2019
  • 4 Anirban Ganguly and Ayan Banerjee, VLSI architecture for analog radix-4 DFT front-end in QAM–OFDM receiver, Analog Integrated Circuits and Signal Processing, Springer, 2019
  • 5 4) Anirban Chakraborty and Ayan Banerjee, A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition, Journal of Real-time Image Processing, Springer, 2019
  • 6 Anirban Ganguly, Anirban Chakraborty and Ayan Banerjee, A Novel VLSI Design of Radix-4 DFT in Current Mode, International Journal of Electronics, Taylor and Francis, 2019
  • 7 Anirban Chakraborty and Ayan Banerjee, Modular and parallel VLSI architecture of multi-dimensional quad core GA co-processor for real time image/ video processing, 65, 180-195, Microprocessor and Microsystems, Elsevier, 2019
  • 8 Debolina Chakraborty, Anirban Chakraborty, Ayan Banerjee and Sekhar Ranjan Bhadra Chaudhuri, A Unified Block-Based Sparse Domain Solution for Quasi-Periodic De-noising from Different Genres of Images with Iterative Filtering, 78(18), 26759-26785, Multimedia Tools and Applications, Springer, 2019
  • 9 Debolina Chakraborty, Milan Kumar Tarafder, Ayan Banerjee and Sekhar Ranjan Bhadra Chaudhuri, Gabor-based spectral domain automated notch-reject filter for quasi-periodic noise reduction from digital images, 78, 1757-1783, Multimedia Tools and Applications, Springer, 2018
  • 10 Debolina Chakraborty, Anirban Chakraborty, Ayan Banerjee and Sekhar Ranjan Bhadra Chaudhur, An Automated Spectral Domain Approach of Quasi-Periodic Denoising in Natural Images using Notch Filtration with Exact Noise Profile, 12, 1150-1163, IET Image Processing, 2018
  • 11 Debolina Chakraborty, Milan Kumar Tarafder, Anirban Chakraborty and Ayan Banerjee, A Proficient Method For Periodic and Quasi Periodic Noise Fading Using Spectral Histogram Thresholding With Sinc Restoration Filter, 70, 1580-1592, International Journal of Electronics and Communications (AEU), Elsevier, 2016
  • 12 Ayan Banerjee and Anindya Sundar Dhar, Pipelined VLSI Architecture Using CORDIC for Transform Domain Equalizer, 70(1), 39-48, Journal of Signal Processing Systems, Springer, 2013
  • 13 Ayan Banerjee and Anindya Sundar Dhar, Novel Architecture for QAM Modulator - Demodulator and its Generalization to Multicarrier Modulation, 29, 351-357, Microprocessors and Microsystems , Elsevier, 2005
  • 14 Ayan Banerjee, Anindya Sundar Dhar and Swapna Banerjee, FPGA realization of CORDIC based FFT Processor for Biomedical Signal Processing, 25, 131-142, Microprocessors and Microsystems, Elsevier, 2001
  • 1 Sayantan Dutta and Ayan Banerjee, Low Latency and Area Efficient Very Large Scale Integration Architecture of 2-Dimensional Bicubic Interpolation using Carry Save Adder Based Fast Multiplier, 686-692, 2020 Fourth International Conference on Inventive Systems and Control (ICISC), 2020
  • 2 Sayantan Dutta and Ayan Banerjee, Low Latency and Area Efficient VLSI Architecture of 2D Bilinear Interpolation using Brent Kung Adder Based Fast Multiplier., 273-278, 2020 Fourth International Conference on Inventive Systems and Control (ICISC), 2020
  • 3 Sayantan Dutta and Ayan Banerjee, Optimal Image Fusion Algorithm using Modified Grey Wolf Optimization amalgamed with Cuckoo Search, Levy Fly and Mantegna Algorithm, 284-290, 2020 2nd International Conference on Innovative Mechanisms for Industry Applications (ICIMIA), 2020
  • 4 Sayantan Dutta and Ayan Banerjee, Optimal Image Fusion Algorithm using Modified Whale Optimization Algorithm Amalgamed with Local Search and BAT Algorithm, 709-715, 2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC), 2020
  • 5 Anirban Chakraborty and Ayan Banerjee, An Adaptive and Automated Image Fusion Algorithm Based on DWT for Real Time Applications, 4th IEEE International Conference on Information Systems and Computer Networks (ISCON 2019), 2019
  • 6 Anirban Ganguly and Ayan Banerjee, Analog VLSI Design of Current Mode DCT for 1D Signal Processing, 4th IEEE International Conference on Information Systems and Computer Networks (ISCON 2019), 2019
  • 7 Debanjana Datta, A. Chaudhuri, Mousumi Bhanja, Baidyanath Ray and Ayan Banerjee, Series Realization of Non-Linear Analog Functions using Current Mode Device, 4th IEEE International Conference on Information Systems and Computer Networks (ISCON 2019), 2019
  • 8 Debanjana Dutta, Mousumi Bhanja, A. Prasad, Baidyanath Ray and Ayan Banerjee, Design of Current-mode High Frequency linear Analog Circuit, IEEE TENSYMP: The IEEE Region 10 Symposium, 2019
  • 9 Debanjana Dutta, S. Agarwal, V. Kumar, M. Raj, Baidyanath Ray and Ayan Banerjee, Design of Current Mode Sigmoid Function and Hyperbolic Tangent Function, 23rd International Symposium on VLSI Design and Test (VDAT-2019), 2019
  • 10 Debanjana Datta, Mousumi Bhanja, A. Chaudhuri, Baidyanath Ray and Ayan Banerjee, Cell-based Coherent Design Methodology for Linear and Non-linear Analog Circuits, IEEE International System-On-Chip Conference (SOCC 2019), September 3-6, 2019, 2019
  • 11 Debanjana Datta, Baidyanath Ray and Ayan Banerjee, Synthesis of Linear and Non-linear Analog Circuits, IEEE International System-On-Chip Conference (SOCC 2019 – PhD Forum) Singapore., 2019
  • 12 Anirban Chakraborty and Ayan Banerjee, Low Latency Semi-iterative CORDIC Algorithm using Normalized Angle Recoding and its VLSI Implementation, 2019 International Conference on Communication and Signal Processing (ICCSP), Chennai, 2019
  • 13 Anirban Chakraborty and Ayan Banerjee, Low Area and Memory Efficient VLSI Architecture of 1D/ 2D DWT For Real Time Image Decomposition, 8th IEEE International Symposium on Embedded Computing and System Design (ISED), 2018
  • 14 Anirban Chakraborty and Ayan Banerjee, Area Efficient Hardware Realisation of QR Decomposition Based 2D Wiener Filter For Audio and Image Signal Denoising With High Accuracy, 4th IEEE International Conference on Computing Communication and Automation (ICCCA), 2018
  • 15 Anirban Ganguly, Anirban Chakraborty and Ayan Banerjee, A Highly Accurate Current Mode Analog Implementation of Radix-2 FFT/IFFT Processor, 8th International Symposium on Embedded Computing and System Design (ISED), 2018
  • 16 Anirban Chakraborty, Debolina Chakraborty and Ayan Banerjee, A Multiplier less VLSI Architecture of Modified Lifting Based 1D/2D DWT using Speculative Adder, 6th IEEE International Conference on Communication and Signal Processing (ICCSP’17), 2017
  • 17 Anirban Chakraborty, Debolina Chakraborty and Ayan Banerjee, A Memory Efficient, High Throughput and Fastest 1D/3D VLSI Architecture for Reconfigurable 9/7 and 5/3 DWT Filters, International Conference on Current Trends in Computer, Electrical, Electronics and Communication (ICCTCEEC’17), IEEE, 2017
  • 18 Debolina Chakraborty, Anirban Chakraborty, Milan Kumar Tarafder, Ayan Banerjee and Sekhar Ranjan Bhadra Chaudhuri, An Efficient Spectral Domain Approach of Periodic Noise Suppression in Digital Images using Gaussian Filtering Profile, International Conference on Current Trends in Computer, Electrical, Electronics and Communication (ICCTCEEC), 2017
  • 19 Mousumi Bhanja, Anirban Ganguly, Debanjana Dutta, Baidyanath Ray and Ayan Banerjee, Reconfigurable Analog Filter Design using Current Mode Device, 1-6, 14th IEEE India Council International Conference (INDICON), Roorkee, 2017
  • 20 Ayan Banerjee and Anindya Sundar Dhar, High Throughput VLSI Architecture for CORDIC Based Pipelined FFT Processor, in Proc. International Joint Conference on Information and Communication Technology,2010 at Bhubaneswar, India, 9-10th, 2010
  • 21 S.P.Maity, P.K.Nandi, Ayan Banerjee and Malay K. Kundu, Low Cost Data Authentication Scheme And Hardware Design, 574-578, Eleventh National Conference on Communication NCC-2005, 2005
  • 22 S.P.Maity, Ayan Banerjee and Malay K. Kundu, An Image-in-image communication scheme and VLSI implementation using FPGA, 6-11, IEEE India Annual Conference 2004, Presented and published, 2004
  • 1 Sirshendu Hore, Tanmay Bhattacharya, Nilanjan Dey, Aboul Ella Hassanien, Ayan Banerjee and S.R. Bhadra Chaudhuri, "A Real Time Dactylology Based Feature Extraction for Selective Image Encryption and Artificial Neural Network " in the book entitled " Image Feature Detectors and Descriptors", Springer International Publishing, Switzerland, 2016
  • 2 Neil Weste, David Harris and Ayan Banerjee, CMOS VLSI Design, A Circuits and Systems perspective, Pearson Education IndiaThird Edition, , 2006
  • 3 Neil Weste, David Harris and Ayan Banerjee, CMOS VLSI Design, A Circuits and Systems perspective, Pearson Education India, Third Edition 2006, 2006
  • Patents


    # Patents Year

    Research Groups


    Anirban Chakraborty
    Ph. D.
    acanirban@gmail.com

    Research:
    VLSI Architecture design for real-time signal and image processing systems

    Debolina Chakaraborty
    Ph. D
    debolina.chk@gmail.com

    Anirban Ganguly
    Ph. D.
    gangulyanirban8@gmail.com

    Research:
    Analog VLSI Design of Transform Domain Signal processing System

    Binit Kumar Pandit
    Ph. D.
    binit7994@gmail.com

    Research:
    VLSI Architecture Design of Convolution Neutral Network Based Imaging Systems

    Debanjana Datta
    Ph. D.
    debanjanadatta2014@gmail.com

    Research:
    Analog VLSI Architecture Design using FPAA

    Citations


    Scopus
    DOCUMENTS CITATION H-INDEX
    23 93 5

    Created: 23 November 2019