Ayan Banerjee

About

Industry Experience:

From 03/03/1999 to 31/07/2000 at

Centre for Development of Telematics (CDOT), New DelhiCentre for Development of Telematics (CDOT), New Delhi

Academic Qualifications

PhD: Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur.
M.Tech: 1999 in Electronics and Electrical Communication Engineering with specialization in Integrated Circuits and Systems Engineering from IIT Kharagpur
B.E.: 1994 in Electronics and Telecommunication Engineering from Bengal Engineering College, Shibpur, Calcutta University

Research Statement

VLSI Architectures for Communication and Biomedical Engineering
VLSI Architectures for Deep Learning based Signal Processing Systems
CORDIC based DSP Architectures
Digital Signal Processing
Digital Image Processing

1 Anirban Ganguly, Debanjana Datta, Mitra, Mousumi Bhanja, Anirban Chakraborty, Ayan Banerjee, A Switched Current Mirror based VLSI Architecture of 1-D DCT for Compressed ECG Signal Acquisition, 1-5, 2024 IEEE Calcutta Conference (CALCON), 2025

2 Anirban Chakraborty, Sayantan Dutta, Indrajit Chakrabarti, Ayan Banerjee, VLSI architecture of stochastic genetic algorithm for real time training of deep neural network, 49 (2), 175, S?dhan?, 2024

3 Moitreya Chaudhury, Binit Kumar Pandit, Ayan Banerjee, A Dynamic Window Size-Based VLSI Architecture Design of Moving Average Filter and Its Vulnerability to Hardware Trojans, 1-6, 2024 28th International Symposium on VLSI Design and Test (VDAT), 2024

4 Akash Ther, Binit Kumar Pandit, Anirban Ganguly, Anirban Chakraborty, Ayan Banerjee, Resource-efficient VLSI Architecture of Softmax Activation Function for Real-time Inference in Deep Learning Applications, 1, 01-05, 2023 International Symposium on Devices, Circuits and Systems (ISDCS), 2023

5 Akash Ther, Binit Kumar Pandit, Ayan Banerjee, VLSI Architecture of Generalized Pooling for Hardware Acceleration of Convolutional Neural Networks, 1, 1-5, 2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC), 2023

6 Rebanta Dey, Binit Kumar Pandit, Anirban Ganguly, Anirban Chakraborty, Ayan Banerjee, Deep Neural Network Based Multi-Object Detection for Real-time Aerial Surveillance, 1, 1-6, 2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC), 2023

7 Binit Kumar Pandit, Ayan Banerjee, 3D EdgeSegNET: a deep neural network framework for simultaneous edge detection and segmentation of medical images, 17 (6), 2981-2989, Signal, Image and Video Processing, 2023

8 Anirban Ganguly, Ayan Banerjee, A Novel Reconfigurable Analog VLSI Architecture of M-point DFT Using Complex Matrix Multiplier and Graph-Based Signal Routing Method, 41, 5201-5225, Circuits, Systems, and Signal Processing, 2022

9 Sampad Chowdhury, Binit Kumar Pandit, Ayan Banerjee, Computation-Efficient and Multiplierless Hardware Realization of Decimation in Time FFT, 1-6, 2022 IEEE Region 10 Symposium (TENSYMP), 2022

10 Deepak Kumar, Anirban Ganguly, Puja Chakraborty, Anirban Chakraborty, Binit Kumar Pandit, Ayan Banerjee, Low power and high precision analog VLSI design of 1-D DCT for real-time application, 1-5, 2022 IEEE Region 10 Symposium (TENSYMP), 2022

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Research Areas

VLSI Architecture Design of Deep Learning Based Signal and Image Processing Systems
VLSI Architecture Design of Image Processing Methods
CORDIC based DSP architectures
VLSI Architectures for Communication and Biomedical Engineering

Teachings

PG Courses

1 Computer Networks 2 Digital Voice and Picture Communication

UG Courses

1 Digital Signal Processing 2 Digital Electronics

Publications

1 Anirban Chakraborty, Sayantan Dutta, Indrajit Chakrabarti, Ayan Banerjee, VLSI architecture of stochastic genetic algorithm for real time training of deep neural network, 49 (2), 175, S?dhan?, 2024

2 Binit Kumar Pandit, Ayan Banerjee, 3D EdgeSegNET: a deep neural network framework for simultaneous edge detection and segmentation of medical images, 17 (6), 2981-2989, Signal, Image and Video Processing, 2023

3 Anirban Ganguly, Ayan Banerjee, A Novel Reconfigurable Analog VLSI Architecture of M-point DFT Using Complex Matrix Multiplier and Graph-Based Signal Routing Method, 41, 5201-5225, Circuits, Systems, and Signal Processing, 2022

4 Debanjana Datta, Ayan Banerjee, Systematic realization of non-linear arithmetic functions using hexagonal Field Programmable Analog Array, 126, 105495, Microelectronics Journal, 2022

5 Baidyanath Ray, Debanjana Datta, Mousumi Bhanja, Ayan Banerjee, Cell-Based Synthesis of Multiple Analog Filter and Oscillator Topologies Employing Graph, 41 (12), 5152-5168, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022

6 Anirban Ganguly, Ayan Banerjee, Precise realization of one-staged 2-D DCT using analog current mode architecture in compressed sensing front-end, 115, 1-9, Microelectronics Journal, 2021

7 Debanjana Datta, Mousumi Bhanja, Ayan Banerjee, Baidyanath Ray, A systematic approach for the design of linear filters and oscillators employing tree representation, 108, 181-203, Analog Integrated Circuits and Signal Processing, 2021

8 Anirban Chakraborty, Ayan Banerjee, Cordic-based high-speed vlsi architecture of transform model estimation for real-time imaging, 29 (1), 215-226, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020

9 Ayan Banerjee and Anindya Sundar Dhar, A Novel Paradigm of CORDIC-Based FFT Architecture Framed on the Optimality of High-Radix Computation., 1-24, Circuits, Systems and Signal Processing, 2020

10 Anirban Chakraborty and Ayan Banerjee, Area and Memory Efficient Tunable VLSI implementation Of DWT Filters for Image Decomposition Using DA, International Journal of Electronics, Taylor and Francis, 2019

11 Anirban Ganguly and Ayan Banerjee, VLSI architecture for analog radix-4 DFT front-end in QAM–OFDM receiver, Analog Integrated Circuits and Signal Processing, Springer, 2019

12 4) Anirban Chakraborty and Ayan Banerjee, A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition, Journal of Real-time Image Processing, Springer, 2019

13 Anirban Ganguly, Anirban Chakraborty and Ayan Banerjee, A Novel VLSI Design of Radix-4 DFT in Current Mode, International Journal of Electronics, Taylor and Francis, 2019

14 Anirban Chakraborty and Ayan Banerjee, Modular and parallel VLSI architecture of multi-dimensional quad core GA co-processor for real time image/ video processing, 65, 180-195, Microprocessor and Microsystems, Elsevier, 2019

15 Debolina Chakraborty, Anirban Chakraborty, Ayan Banerjee and Sekhar Ranjan Bhadra Chaudhuri, A Unified Block-Based Sparse Domain Solution for Quasi-Periodic De-noising from Different Genres of Images with Iterative Filtering, 78(18), 26759-26785, Multimedia Tools and Applications, Springer, 2019

16 Debolina Chakraborty, Milan Kumar Tarafder, Ayan Banerjee and Sekhar Ranjan Bhadra Chaudhuri, Gabor-based spectral domain automated notch-reject filter for quasi-periodic noise reduction from digital images, 78, 1757-1783, Multimedia Tools and Applications, Springer, 2018

17 Debolina Chakraborty, Anirban Chakraborty, Ayan Banerjee and Sekhar Ranjan Bhadra Chaudhur, An Automated Spectral Domain Approach of Quasi-Periodic Denoising in Natural Images using Notch Filtration with Exact Noise Profile, 12, 1150-1163, IET Image Processing, 2018

18 Debolina Chakraborty, Milan Kumar Tarafder, Anirban Chakraborty and Ayan Banerjee, A Proficient Method For Periodic and Quasi Periodic Noise Fading Using Spectral Histogram Thresholding With Sinc Restoration Filter, 70, 1580-1592, International Journal of Electronics and Communications (AEU), Elsevier, 2016

19 Ayan Banerjee and Anindya Sundar Dhar, Pipelined VLSI Architecture Using CORDIC for Transform Domain Equalizer, 70(1), 39-48, Journal of Signal Processing Systems, Springer, 2013

20 Ayan Banerjee and Anindya Sundar Dhar, Novel Architecture for QAM Modulator - Demodulator and its Generalization to Multicarrier Modulation, 29, 351-357, Microprocessors and Microsystems , Elsevier, 2005

21 Ayan Banerjee, Anindya Sundar Dhar and Swapna Banerjee, FPGA realization of CORDIC based FFT Processor for Biomedical Signal Processing, 25, 131-142, Microprocessors and Microsystems, Elsevier, 2001

2 Moitreya Chaudhury, Binit Kumar Pandit, Ayan Banerjee, A Dynamic Window Size-Based VLSI Architecture Design of Moving Average Filter and Its Vulnerability to Hardware Trojans, 1-6, 2024 28th International Symposium on VLSI Design and Test (VDAT), 2024

3 Akash Ther, Binit Kumar Pandit, Anirban Ganguly, Anirban Chakraborty, Ayan Banerjee, Resource-efficient VLSI Architecture of Softmax Activation Function for Real-time Inference in Deep Learning Applications, 1, 01-05, 2023 International Symposium on Devices, Circuits and Systems (ISDCS), 2023

4 Akash Ther, Binit Kumar Pandit, Ayan Banerjee, VLSI Architecture of Generalized Pooling for Hardware Acceleration of Convolutional Neural Networks, 1, 1-5, 2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC), 2023

5 Rebanta Dey, Binit Kumar Pandit, Anirban Ganguly, Anirban Chakraborty, Ayan Banerjee, Deep Neural Network Based Multi-Object Detection for Real-time Aerial Surveillance, 1, 1-6, 2023 11th International Symposium on Electronic Systems Devices and Computing (ESDC), 2023

6 Sampad Chowdhury, Binit Kumar Pandit, Ayan Banerjee, Computation-Efficient and Multiplierless Hardware Realization of Decimation in Time FFT, 1-6, 2022 IEEE Region 10 Symposium (TENSYMP), 2022

7 Deepak Kumar, Anirban Ganguly, Puja Chakraborty, Anirban Chakraborty, Binit Kumar Pandit, Ayan Banerjee, Low power and high precision analog VLSI design of 1-D DCT for real-time application, 1-5, 2022 IEEE Region 10 Symposium (TENSYMP), 2022

8 Binit Kumar Pandit, Ayan Banerjee, VLSI architecture of sigmoid activation function for rapid prototyping of machine learning applications, 117-122, 2021 IEEE International Symposium on Smart Electronic Systems (iSES), 2021

9 Sayantan Dutta and Ayan Banerjee, Low Latency and Area Efficient Very Large Scale Integration Architecture of 2-Dimensional Bicubic Interpolation using Carry Save Adder Based Fast Multiplier, 686-692, 2020 Fourth International Conference on Inventive Systems and Control (ICISC), 2020

10 Sayantan Dutta and Ayan Banerjee, Low Latency and Area Efficient VLSI Architecture of 2D Bilinear Interpolation using Brent Kung Adder Based Fast Multiplier., 273-278, 2020 Fourth International Conference on Inventive Systems and Control (ICISC), 2020

11 Sayantan Dutta and Ayan Banerjee, Optimal Image Fusion Algorithm using Modified Grey Wolf Optimization amalgamed with Cuckoo Search, Levy Fly and Mantegna Algorithm, 284-290, 2020 2nd International Conference on Innovative Mechanisms for Industry Applications (ICIMIA), 2020

12 Sayantan Dutta and Ayan Banerjee, Optimal Image Fusion Algorithm using Modified Whale Optimization Algorithm Amalgamed with Local Search and BAT Algorithm, 709-715, 2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC), 2020

13 Anirban Ganguly, Ayan Banerjee, VLSI design of analog DFT processor for demodulation of QAM-OFDM signal, 1-5, 2019 IEEE 5th International Conference for Convergence in Technology (I2CT), 2019

14 Anirban Chakraborty and Ayan Banerjee, An Adaptive and Automated Image Fusion Algorithm Based on DWT for Real Time Applications, 4th IEEE International Conference on Information Systems and Computer Networks (ISCON 2019), 2019

15 Anirban Ganguly and Ayan Banerjee, Analog VLSI Design of Current Mode DCT for 1D Signal Processing, 4th IEEE International Conference on Information Systems and Computer Networks (ISCON 2019), 2019

16 Debanjana Datta, A. Chaudhuri, Mousumi Bhanja, Baidyanath Ray and Ayan Banerjee, Series Realization of Non-Linear Analog Functions using Current Mode Device, 4th IEEE International Conference on Information Systems and Computer Networks (ISCON 2019), 2019

17 Debanjana Dutta, Mousumi Bhanja, A. Prasad, Baidyanath Ray and Ayan Banerjee, Design of Current-mode High Frequency linear Analog Circuit, IEEE TENSYMP: The IEEE Region 10 Symposium, 2019

18 Debanjana Dutta, S. Agarwal, V. Kumar, M. Raj, Baidyanath Ray and Ayan Banerjee, Design of Current Mode Sigmoid Function and Hyperbolic Tangent Function, 23rd International Symposium on VLSI Design and Test (VDAT-2019), 2019

19 Debanjana Datta, Mousumi Bhanja, A. Chaudhuri, Baidyanath Ray and Ayan Banerjee, Cell-based Coherent Design Methodology for Linear and Non-linear Analog Circuits, IEEE International System-On-Chip Conference (SOCC 2019), September 3-6, 2019, 2019

20 Debanjana Datta, Baidyanath Ray and Ayan Banerjee, Synthesis of Linear and Non-linear Analog Circuits, IEEE International System-On-Chip Conference (SOCC 2019 – PhD Forum) Singapore., 2019

21 Anirban Chakraborty and Ayan Banerjee, Low Latency Semi-iterative CORDIC Algorithm using Normalized Angle Recoding and its VLSI Implementation, 2019 International Conference on Communication and Signal Processing (ICCSP), Chennai, 2019

22 Anirban Chakraborty and Ayan Banerjee, Low Area and Memory Efficient VLSI Architecture of 1D/ 2D DWT For Real Time Image Decomposition, 8th IEEE International Symposium on Embedded Computing and System Design (ISED), 2018

23 Anirban Chakraborty and Ayan Banerjee, Area Efficient Hardware Realisation of QR Decomposition Based 2D Wiener Filter For Audio and Image Signal Denoising With High Accuracy, 4th IEEE International Conference on Computing Communication and Automation (ICCCA), 2018

24 Anirban Ganguly, Anirban Chakraborty and Ayan Banerjee, A Highly Accurate Current Mode Analog Implementation of Radix-2 FFT/IFFT Processor, 8th International Symposium on Embedded Computing and System Design (ISED), 2018

25 Anirban Chakraborty, Debolina Chakraborty and Ayan Banerjee, A Multiplier less VLSI Architecture of Modified Lifting Based 1D/2D DWT using Speculative Adder, 6th IEEE International Conference on Communication and Signal Processing (ICCSP’17), 2017

26 Anirban Chakraborty, Debolina Chakraborty and Ayan Banerjee, A Memory Efficient, High Throughput and Fastest 1D/3D VLSI Architecture for Reconfigurable 9/7 and 5/3 DWT Filters, International Conference on Current Trends in Computer, Electrical, Electronics and Communication (ICCTCEEC’17), IEEE, 2017

27 Debolina Chakraborty, Anirban Chakraborty, Milan Kumar Tarafder, Ayan Banerjee and Sekhar Ranjan Bhadra Chaudhuri, An Efficient Spectral Domain Approach of Periodic Noise Suppression in Digital Images using Gaussian Filtering Profile, International Conference on Current Trends in Computer, Electrical, Electronics and Communication (ICCTCEEC), 2017

28 Mousumi Bhanja, Anirban Ganguly, Debanjana Dutta, Baidyanath Ray and Ayan Banerjee, Reconfigurable Analog Filter Design using Current Mode Device, 1-6, 14th IEEE India Council International Conference (INDICON), Roorkee, 2017

29 Ayan Banerjee and Anindya Sundar Dhar, High Throughput VLSI Architecture for CORDIC Based Pipelined FFT Processor, in Proc. International Joint Conference on Information and Communication Technology,2010 at Bhubaneswar, India, 9-10th, 2010

30 S.P.Maity, P.K.Nandi, Ayan Banerjee and Malay K. Kundu, Low Cost Data Authentication Scheme And Hardware Design, 574-578, Eleventh National Conference on Communication NCC-2005, 2005

31 S.P.Maity, Ayan Banerjee and Malay K. Kundu, An Image-in-image communication scheme and VLSI implementation using FPGA, 6-11, IEEE India Annual Conference 2004, Presented and published, 2004

1 Sirshendu Hore, Tanmay Bhattacharya, Nilanjan Dey, Aboul Ella Hassanien, Ayan Banerjee and S.R. Bhadra Chaudhuri, "A Real Time Dactylology Based Feature Extraction for Selective Image Encryption and Artificial Neural Network " in the book entitled " Image Feature Detectors and Descriptors", Springer International Publishing, Switzerland, 2016

2 Neil Weste, David Harris and Ayan Banerjee, CMOS VLSI Design, A Circuits and Systems perspective, Pearson Education IndiaThird Edition, , 2006

3 Neil Weste, David Harris and Ayan Banerjee, CMOS VLSI Design, A Circuits and Systems perspective, Pearson Education India, Third Edition 2006, 2006