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    • Admission Notices

    Surajeet Ghosh

    Academic Qualifications


    • Ph.D. (Engineering), Jadavpur University, Kolkata, India
    • M.E. (Computer Science and Engineering), Maulana Abul Kalam Azad University of Technology, (Formerly West Bengal University of Technology), Kolkata, India
    • B.Tech. (Computer Science and Technology), University of Kalyani, Kalyani, West Bengal, India

    Research Statement


    Computing Environment:

    • Hardware Accelerators for Machine Learning Applications
    • Machine Learning for Embedded Systems
    • Neuromorphic Computing, Custom Computing
    • Computational Architecture for Next Generation Sequencing
    • FPGA Based Embedded Systems Design
    Hardware Accelerator for Short-Read DNA Sequence Alignment
    Hardware Accelerator for
    Short-Read DNA Sequencing

     
    Multiprocessor Architecture for Multiple Pair-wise Sequence Alignment
    Multiprocessor Architecture for Multiple Pair-wise Sequence Alignment

    Computer Network and Internet of Things (IoT):

    • Machine Learning Based Optimization in IoT Protocol
    • IPv6 Routing Protocol for Low-Power and Lossy Networks (RPL)
    • Hardware Architecture for Network Routing Schemes
    • Routing Protocol for IoT Networks

    		  

     

    Dr. Ardhendu Sarkar (Ph.D. Scholar, Degree awarded in December 2024)
    His Ph.D. thesis has been recognized as a High-Quality Ph.D. Research Work in Ph.D. Forum at the 62-nd IEEE Design Automation Conference (DAC) 2025. In recognition of his outstanding contributions, he has received an invitation along with a Travel Grant to present his research work at this prestigious event, held from June 22–25, 2025, in San Francisco, USA.

    Latest Publications


  • 1 S. Mandal and S. Ghosh, Hardware Accelerator for Short-Read DNA Sequence Alignment Using Burrows-Wheeler Transformation, Early Access, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025
  • 2 A. Sarkar and S. Ghosh, Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pair-Wise Sequence Alignment, Vol. 43, No. 8, pp. 2365-2378, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024
  • 3 S. Ghosh, CB-ED-RPL: Coordinator-Based Energy-Efficient Dynamic RPL for IoT Networks, Wireless Personal Communications, Springer Nature, 2023
  • 4 S. Ghosh and S. S. Ray, O(N) Memory-Free Hardware Architecture for Burrows-Wheeler Transform, Vol. 72, No. 7 (Early Access 2022), pp. 2080-2093, IEEE Transactions on Computers, 2023
  • 5 S. Ray and S. Ghosh, k-Degree Parallel Comparison-free Hardware Sorter for Complete Sorting, Vol. 42, No. 5, (Early Access 2022), pp. 1438-1449, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023
  • 6 S. Ghosh and A. Chand, CB-RPL: Coordinator-Based RPL for Energy Efficient Routing Mechanism, 231-236, 2022 IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS), Gandhinagar, December, 2022
  • 7 S. S. Ray, D. Adak and S. Ghosh, Worst Case O(N) Comparison-Free Hardware Sorting Engine, vol. 41, no. 10, pp. 3332-3345, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (Early Access 2021), 2022
  • 8 S. S. Ray, S. Ghosh and B. Sardar, Memory Efficient Hash-Based Longest Prefix Matching Architecture with Zero False +ve and Nearly Zero False -ve Rate for IP Processing, Vol. 71, No. 6, pp. 1261 - 1275, IEEE Transactions on Computers, (Early Access 2021), 2022
  • 9 A. Sarkar, S. Ghosh and S. Saha Ray, A Hardware-Based Memory-Efficient Solution for Pair-Wise Compact Sequence Alignment, 1-12, IETE Journal of Research, Taylor & Francis, 2021
  • 10 A. Sarkar, S. Banerjee and S. Ghosh, An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological Sequence Alignment, Vol. 28, No. 12, pp. 2598 – 2611, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020
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    Research Areas


    • Machine Learning Based Optimization for IoT Protocol
    • Hardware Accelerators for Machine Learning Applications
    • IPv6 Routing Protocol for Low-Power and Lossy Networks (RPL)
    • Machine Learning for Embedded Systems
    • Routing Protocol for IoT Networks
    • FPGA Based Embedded Systems Design
    • Hardware Architecture for Network Routing Schemes
    • Computational Architecture for Next Generation Sequencing

    Publications


  • 1 S. Mandal and S. Ghosh, Hardware Accelerator for Short-Read DNA Sequence Alignment Using Burrows-Wheeler Transformation, Early Access, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025
  • 2 A. Sarkar and S. Ghosh, Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pair-Wise Sequence Alignment, Vol. 43, No. 8, pp. 2365-2378, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024
  • 3 S. Ghosh, CB-ED-RPL: Coordinator-Based Energy-Efficient Dynamic RPL for IoT Networks, Wireless Personal Communications, Springer Nature, 2023
  • 4 S. Ghosh and S. S. Ray, O(N) Memory-Free Hardware Architecture for Burrows-Wheeler Transform, Vol. 72, No. 7 (Early Access 2022), pp. 2080-2093, IEEE Transactions on Computers, 2023
  • 5 S. Ray and S. Ghosh, k-Degree Parallel Comparison-free Hardware Sorter for Complete Sorting, Vol. 42, No. 5, (Early Access 2022), pp. 1438-1449, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023
  • 6 S. S. Ray, D. Adak and S. Ghosh, Worst Case O(N) Comparison-Free Hardware Sorting Engine, vol. 41, no. 10, pp. 3332-3345, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (Early Access 2021), 2022
  • 7 S. S. Ray, S. Ghosh and B. Sardar, Memory Efficient Hash-Based Longest Prefix Matching Architecture with Zero False +ve and Nearly Zero False -ve Rate for IP Processing, Vol. 71, No. 6, pp. 1261 - 1275, IEEE Transactions on Computers, (Early Access 2021), 2022
  • 8 A. Sarkar, S. Ghosh and S. Saha Ray, A Hardware-Based Memory-Efficient Solution for Pair-Wise Compact Sequence Alignment, 1-12, IETE Journal of Research, Taylor & Francis, 2021
  • 9 A. Sarkar, S. Banerjee and S. Ghosh, An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological Sequence Alignment, Vol. 28, No. 12, pp. 2598 – 2611, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020
    • 10 S. K. Ray and S. Ghosh, Binarily Gapped Binary Insertion Sorting Technique, 64(3), 337-346, Institution of Electronics and Telecommunication Engineers (IETE) Journal of Research, 2018 11 S. Saha Ray, K. Das and S. Ghosh, A RAM-Based MAC Table with Two-Tier Security at Layer 2, 62(4), 435-445, IETE Journal of Research, 2016 12 S. S. Ray, S. Ghosh and B. Sardar, SRAM Based Novel Hardware Architecture for Longest Prefix Matching for IP Route Lookup, 32(3), 359 – 371, Photonic Network Communications – Springer, 2016
  • 13 S. Ghosh, S. Saha Ray, 4th Generation Progrqammable Logic Computing: A Road Map, 24(6), 439 - 452, IETE Technical Review, 2007
  • 1 S. Ghosh and A. Chand, CB-RPL: Coordinator-Based RPL for Energy Efficient Routing Mechanism, 231-236, 2022 IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS), Gandhinagar, December, 2022
  • 2 A. Sarkar, K. Ray, D. Chowdhury, K. Sahu, S. Kundu and S. Ghosh, Time and Space Efficient Optimal Pairwise Sequence Alignment using GPU, 2019 IEEE Region 10 Conference (TENCON), Kochi, Kerala, 2019
  • 3 S. Ghosh, S. Dasgupta, and S. Saha Ray, A Comparison-free Hardware Sorting Engine, 586-591, 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Miami, Florida, 2019
  • 4 S. Ghosh and A. Sarkar, An FPGA-Based Processor for Compact Sequence Alignment, IEEE International conference on Electronics, Communication and Aerospace Technology (IEEE ICECA 2018), 2018
  • 5 D. Sharma, A. Gupta, A. K. Layek and S. Ghosh, Movable Wireless Access Point for IoT-Based Home Automation, 2018 15th IEEE India Council International Conference (INDICON), Coimbatore, India, December 16 – 18., 2018
  • 6 A. Sarkar and S. Ghosh, A Coarse-Grained Pipeline Architecture for Sequence Alignment, 2018 15th IEEE India Council International Conference (INDICON), Coimbatore, India, December 16 – 18, 2018., 2018
  • 7 S. Saha Ray, S. Singh, C. Sengupta, S. Ghosh and B. Sardar, A Fine-grained Integrated IP Lookup Engine for Multigigabit IP Processing, 2018 IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS), Indore, India, 16-19 December 2018., 2018
  • 8 S. Ghosh, S. Kesharwani, V. Mishra and S. S. Ray, Hybrid trie based approach for longest prefix matching in IP packet processing, 1532-1537, TENCON 2017 - IEEE Region 10 Conference, 2017
    • 9 S. Ghosh and M. Baliyan, A Hash Based Architecture of Longest Prefix Matching for Fast IP Processing, 228 – 231, TENCON 2016 - 2016 IEEE Region 10 Conference, Singapore, 2016 10 S. Saha Ray, A. Banerjee, A. Datta and S. Ghosh, A Memory Efficient DNA Sequence Alignment Technique Using Pointing Matrix, 3559 – 3562, TENCON 2016 - 2016 IEEE Region 10 Conference, Singapore, 2016 11 S. S. Ray, N. Srivastava and S. Ghosh, A Hardware-Based High-Throughput DNA Sequence Alignment Scheme, 1 -6, India Conference (INDICON), 2016 Annual IEEE, Bengaluru, 2016, 2016 12 S. Ghosh, S. Mandal and S. Saha Ray, A scalable high-throughput pipeline architecture for DNA sequence alignment, 1-6, TENCON 2015 - 2015 IEEE Region 10 Conference, Macao, 2015, 2015 13 S. S. Ray, S. Ghosh and B. Sardar, SRAM based longest prefix matching approach for multigigabit IP processing, 1-6, 2015 IEEE International Conference on Advanced Networks and Telecommuncations Systems (ANTS), Kolkata, 2015, 2015 14 S. S. Ray, A. Chatterjee, S. Ghosh, A novel approach for prefix minimization using Ternary Trie (PMTT) for packet classification, 1-6, TENCON 2014 - 2014 IEEE Region 10 Conference, 2014 15 S. S. Ray, A. Bhattacharya, S. Ghosh, A fast range matching architecture with unit storage expansion ratio and high memory utilization using SBiCAM for packet classification, 1-6, India Conference (INDICON), 2014 Annual IEEE, 2014 16 S. S. Ray, S. Ghosh, R. Prasad, Low-cost hierarchical memory-based pipelined architecture for DNA sequence matching, 1-6, India Conference (INDICON), 2014 Annual IEEE, 2014 17 S. Ghosh, S. S. Ray, S. Mandal, High Through-put Scalable Query Processing Architecture using STCAM, 650-653, Proc. of IEEE International Conference on Computational Intelligence and Computing Research, (Available in IEEE Xplore Digital Library), Madurai 26th-28th Dec. 2013, Print ISBN: 978-1-4799-1594-1, 2013 18 S. S. Ray, A. Chatterjee, S. Ghosh, A Hierarchical High-throughput and Low Power Architecture for Longest Prefix Matching for Packet Forwarding, 628-631, Proc. of IEEE International Conference on Computational Intelligence and Computing Research, (Available in IEEE Xplore Digital Library), Madurai 26th-28th Dec. 2013. Print ISBN: 978-1-4799-1594-1, 2013 19 S. Saha Ray, S. Ghosh, Smart Ternary Content Addressable Memory (STCAM) Architecture, 434 – 438, Ieee International Conference on Advanced Communication Control and Computing Technologies (Icaccct) (Available in IEEE Xplore Digital Library), Ramanathapuram, 2012 20 S. Ghosh, J. Ghosh, S. Saha Ray, Architecture of Configurable K-way C-access Interleaved Memory, nternational Conference on Process Automation Control and Computing (ICPACC) (Available in IEEE Xplore Digital Library), Coimbatore, 20-22 July 2011. Print ISBN: 978-1-61284-765-8, 2011
  • 21 S. K. Ray, S. Ghosh, Low-Cost dictionary machine using RAM -Based CAM, 559-566, International Conference on Advanced Computing (ICAC 09), Tiruchirappalli, Aug. 6-8, 2009
  • 22 S. Ghosh, S. Saha Ray, Register Size Programmable Autoconfigured Register Size for RISC Processors, Proceedings of International Conference on Embedded Systems and VLSI Design (ICVLSI), Chennai, Feb 14-16, 2008, 2008
  • 1 A. Sarkar, S. Mandal and S. Ghosh, Hardware and Software Based Sequence Alignment Approaches: A Survey, CRC Press, Taylor & Francis, 2023
  • 2 S. Mandal and S. Ghosh, Biological Sequence Alignment using Burrows- Wheeler Transformation: An Implementation Roadmap, CRC Press, Taylor & Francis, 2023

    • Patents


    # Patents Year
    1 Intelligent Associative Memory (IAM) System 2023

    Member


    The Institution of Electronics and Telecommunication Engineers (IETE), Life Fellow
    IEEE Communications Society
    IEEE Computer Society
    Institute of Electrical and Electronics Engineers (IEEE)

    Projects


    • Design and Implementation of a Comparison-Free Scalable High-Throughput Energy-Efficient Hardware Sorting Engine for FPGA-Based Embedded System Applications, Sponsored
      Completed
    • Design and Implementation of Pipeline Architecture for DNA Sequence Alignment, Sponsored
      Completed

    Awards


    • Ph.D. Thesis of Dr. Ardhendu Sarkar has been recognized as a High-Quality Ph.D. Research Work in Ph.D. Forum at the 62-nd IEEE Design Automation Conference (DAC) 2025. He has received an invitation along with a Travel Grant to present his research work., Year: 2025
    • Gowri Memorial Award (GMA) for the best paper on topic of General Interest, "4th Generation Programmable Logic Computing: A Road Map" published in IETE Technical Review, Year: 2007
    • Best Paper Award for the paper entitled "Low-Cost dictionary machine using RAM-Based CAM", International Conference on Advanced Computing, Year: 2009
    • Best Paper Award for the paper entitled "A Hierarchical High-throughput and Low Power Architecture for Longest Prefix Matching for Packet Forwarding" presented at 2013 IEEE International Conference on Computational Intelligence and Computing Research, Year: 2013

    Research Groups


    Som Banerjee
    M. Tech.
    sombanerjeeofficial@gmail.com

    Research:
    Hardware Architecture for Biological Sequence Alignment

    Dulal Adak
    M. Tech.
    adak.dulal.92@gmail.com

    Research:
    Hardware Architecture for High Speed Sorting Operations

    Sriparna Mandal
    Ph. D.
    2021csp001.sriparna@students.iiests.ac.in

    Sayani Chandra
    Ph. D.
    2024csp001.sayani@students.iiests.ac.in

    Arijit Bagdi
    Ph. D.
    2024csp006.arijit@students.iiests.ac.in

    Ardhendu Sarkar
    M. Tech.
    ardhendu.iiest@gmail.com

    Research:
    Hardware Architecture for Biological Sequence Alignment

    Created: 23 November 2019