Dr. Subiman Chatterjee is working with Electronics and Telecommunication Engineering Department, IIEST, Shibpur since September, 2023. He has completed his Ph.D. degree in the area of VLSI designing from Department of Electronics Engineering, IIT (BHU), Varanasi. His research interests include VLSI architectures for signal processing, digital circuits and systems design, algorithms and architectures for high efficiency video coding, versatile video coding, image and video signal processing.
Ph.D. (Electronics Engineering)
Dissertation: VLSI Architectures for the Core Transform in High Efficiency Video Coding,
Indian Institute of Technology (BHU), Varanasi
M. Tech. (Electronics Engineering)
Dissertation: A RISC Architecture with Low Cost Error Correction Mechanism
Indian Institute of Technology (BHU), Varanasi
B. Tech. (Electronics and Communication Engineering),
West Bengal University of Technology, Kolkata
His research interests are as follows:
- VLSI architectures for signal processing,
- Digital circuits and systems design,
- Algorithms and architectures for high efficiency video coding/versatile video coding,
- Image/video signal processing,
1
S Chatterjee, D Bhardwaj, B Prasad, K Sarawadekar, Scalable Matrix Decomposition-Based Less-Complex HEVC Transform Architecture, Early Access, IEEE Transactions on Consumer Electronics, 2024
2
S. Chatterjee, K. Sarawadekar, Exploiting Trigonometric Properties to Optimize Higher Order DCT Architecture in HEVC, 30, 3598-3607, IEEE Transactions on Circuits and Systems for Video Technology, 2020
3
S. Chatterjee and K. Sarawadekar, WHT and Matrix Decomposition Based Approximated IDCT Architecture for HEVC, 66, 1043-1047, IEEE Transactions on Circuits and Systems II: Express Briefs, 2019
4
S. Chatterjee and K. Sarawadekar, Approximated Core Transform Architectures for HEVC Using WHT Based Decomposition Method, 66, 4296-4308, IEEE Transactions on Circuits and Systems–I: Regular Papers, 2019
5
S. Chatterjee and K. Sarawadekar, An Optimized Architecture of HEVC Core Transform using Real-valued DCT Coefficients, 65, 2052-2056, IEEE Transactions on Circuits and Systems II: Express Briefs, 2018
6
S. Chatterjee and K. Sarawadekar, “A low cost, constant throughput and reusable 8×8 DCT architecture for HEVC, IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, 2016
7
S. Chatterjee and K. Sarawadekar, Constant throughput HEVC core transform design, IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS), Abu Dhabi, 2016
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