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Surajit Kumar Roy

About


Dr. Surajit Kumar Roy is currently an Associate Professor in the Department of Information Technology, Indian Institute of Engineering Science and Technology, Shibpur, India. He received the B.Sc. (Hons. in Physics) from Calcutta University, India. He also received a Bachelor of Technology in computer science and engineering and subsequently a Master of Technology in computer science and engineering from Calcutta University, India in 2002 and 2004. He was awarded a Ph.D. degree from the Indian Institute of Engineering Science and Technology (IIEST), Shibpur.

Academic Qualifications


•    PhD (IIEST,)
•    M.Tech., Computer Science and Engineering, University of Calcutta
•    B.Tech., Computer Science and Engineering, University of Calcutta
•    B.Sc., Physics (H), University of Calcutta

 

Research Statement


His research interest includes VLSI testing, 3D Integrated Circuits, TSV testing and recovery Embedded Systems, Hardware security. He was a recipient of the Best Ph.D. Thesis Award in ATS’16. He has contributed several research articles in peer-reviewed international journals and conferences.

 

Latest Publications


  • 1 Tapabrata Dhar, Surajit Kumar Roy and Chandan Giri, Hardware Trojan Detection by Stimulating Transitions in Rare Nets, 537-538, VLSI Design Conference (VLSID), 2019
  • 2 Dilip Kumar Maity, Surajit Kumar Roy and Chandan Giri, Identification of Random/Clustered TSV Defects in 3D IC during Pre-bond Testing, Accepted for publication in Journal of Electronic Testing:Theory and Applications (JETTA), Springer, 2019
  • 3 Tapabrata Dhar, Surajit Kumar Roy and Chandan Giri, Detecting Hardware Trojans by Reducing Rarity of Transitions in Ics, 173-185, VDAT, 2018
  • 4 Dilip Kumar Maity, Surajit Kumar Roy and Chandan Giri, Identification of Faulty TSVs in 3D IC during Pre-bond Testing, 109-114, VLSI Design Conference (VLSID), 2018
  • 5 Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri and HafizurRahaman, Identification of Faulty TSV with a Built-In Self-Test Mechanism, 1-6, Asian Test Symposium (ATS), 2018
  • 6 Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri and HafizurRahaman, Modeling and Analysis of Transient Heat for 3D IC Conference, 363-375, VDAT, 2017
  • 7 Surajit Kumar Roy and Chandan Giri, Design-for-test and test time optimization for 3D SOCs, 1-10, International Test Conference (ITC), 2017
  • 8 Sudeep Ghosh, Surajit Kumar Roy,Hafizur Rahaman and Chandan Giri, TSV repairing for 3D ICs using redundant TSV, 1-5, ISED, 2017
  • 9 Surajit Kumar Roy, Chandan Giri and HafizurRahaman, Optimization of Test Wrapper for TSV Based 3D SOCs, 32(5), 511-529, journal of Electronic Testing, 2016
  • 10 Surajit Kumar Roy, Chandan Giri and Hafizur Rahaman, Optimization of Test Architecture in 3D Stacked ICs for Partial Stack/Complete Stack using Hard SOCs, 9(5), 268-274, Journal of IEEE Computer and Digital Techniques, 2015
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    Research Areas


    • Hardware Security
    • Reliability and Yield of 3D IC
    • Design-for-testability of 3D IC
    • 3D IC Testing

    Publications


  • 1 Dilip Kumar Maity, Surajit Kumar Roy and Chandan Giri, Identification of Random/Clustered TSV Defects in 3D IC during Pre-bond Testing, Accepted for publication in Journal of Electronic Testing:Theory and Applications (JETTA), Springer, 2019
  • 2 Surajit Kumar Roy, Chandan Giri and HafizurRahaman, Optimization of Test Wrapper for TSV Based 3D SOCs, 32(5), 511-529, journal of Electronic Testing, 2016
  • 3 Surajit Kumar Roy, Chandan Giri and Hafizur Rahaman, Optimization of Test Architecture in 3D Stacked ICs for Partial Stack/Complete Stack using Hard SOCs, 9(5), 268-274, Journal of IEEE Computer and Digital Techniques, 2015

    Patents


    # Patents Year

    Created: 23 November 2019