Research Area : Semiconductor Devices, Electrodynamic Screening
Technical Skills : Semiconductor Device process Design and Numerical Device Simulation using Sentaurus TCAD process and device simulators.
Experimental Skills : N.A.
Presently working at : Asutosh College, under University of Calcutta as Assistant Professor, Department of Electronics, August, 2019 – till date.
Work Experience :
Full time Faculty Member (CWTT – Govt of WB approved), Department of Electronic Science, August, 2010 – July, 2019.
Taught different topics in UG course, guide students in laboratory experiments, arrange student seminars, act as question paper setter, examiner/scrutineer in theoretical and practical examinations of West Bengal State University, and other departmental administrative jobs.
Faculty Member, School of VLSI Technology, January, 2017 – June, 2017.
Taught VLSI Technology in M.Tech VLSI course.
Part Time lecturer, Department of Electronics, July, 2010 – November, 2011.
Taught Electronic Science to UG students.
INDUSTRY EXPERIENCE :
Assistant System Engineer, August, 2008 – August, 2010.
Prepared and executed different codes in Hyperion system for smooth running of client’s business. Supported the team during the version update of Hyperion system in the client environment.
BOOK :
Dr. Kunal Sinha, Dr. Sanatan Chattopadhyay, Prof. Hafizur Rahaman; “Performance-Aware Stress Engineering for Nano-scaled FETs”; LAP LAMBERT Academic Publishing; ISBN No.: 978-613-9-58544-1.
BOOK CHAPTER :
Kunal Sinha, “STRAIN ENGINEERING IN MODERN FIELD EFFECT TRANSISTORS”, S. L. Tripathy et al. (eds.), Electrical and Electronic Devices, Circuits, and Materials: Technological Challenges and Solutions (Scrivener Publishing, Wiley), (Accepted).
PATENT :
Kunal Sinha, Sanatan Chattopadhyay, Partha Sarathi Gupta, Hafizur Rahaman; “Method to analyze Channel Stress in Ge FinFET Architecture and architecture thereof”; Indian Patent Application filed on 31st May, 2018, Application No.: 201831020551.
JOURNAL :
“A technique to incorporate both tensile and compressive channel stress in Ge FinFET architecture”, Kunal Sinha, Sanatan Chattopadhyay, Partha Sarathi Gupta, Hafizur Rahaman; Journal of Computational Electronics (2017), Volume 16, Issue 3, pp 620–630, September 2017. doi: 10.1007/s10825-017-1003-x. (Impact Factor: 1.526)
“Investigating the performance of SiGe embedded dual source p-FinFET architecture”, Kunal Sinha, Partha Sarathi Gupta, Sanatan Chattopadhyay, Hafizur Rahaman; Superlattices and Microstructures, Volume 98, October 2016, Pages 37–45, doi:10.1016/j.spmi.2016.08.004.(Impact Factor: 2.123)
“A Device Simulation based Investigation on Dielectrically Modulated Fringing Field Effect Transistor for Biosensing Applications”, Sayan Kanungo, Sanatan Chattopadhyay, Kunal Sinha, Partha Sarathi Gupta, Hafizur Rahaman, IEEE Sensors Journal, Volume 17, Issue 5, 2017, Pages 1399-1406.(Impact Factor: 2.512)
“An optoelectronic band-to-band tunnel transistor for near-infrared sensing applications: Device physics, modeling, and simulation”, Partha Sarathi Gupta, Hafizur Rahaman, Kunal Sinha, Sanatan Chattopadhyay, Journal of Applied Physics, Volume 120, Issue 8, 2016, Pages 084510.(Impact Factor: 2.068)
“Study and analysis of the effects of SiGe source and pocket-doped channel on sensing performance of dielectrically modulated tunnel FET-based biosensors”, Sayan Kanungo, Sanatan Chattopadhyay, Partha Sarathi Gupta, Kunal Sinha, Hafizur Rahaman, IEEE Transactions on Electron Devices, Volume 63, Issue 6, 2016, Pages 2589-2596.(Impact Factor: 2.605)
“An extremely low sub-threshold swing UTB SOI tunnel-FET structure suitable for low-power applications”, Partha Sarathi Gupta, Sayan Kanungo, Hafizur Rahaman, Kunal Sinha, Partha Sarathi Dasgupta, International Journal of Applied Physics and Mathematics, Volume 2, Issue 4, 2012, Page 240.
CONFERENCE :
“Incorporation of Tensile and Compressive Channel Stress by Modulating SiGe Stressor length in Embedded Source/Drain Si-FinFET Architecture”, Kunal Sinha, Partha Sarathi Gupta, Hafizur Rahaman, Sanatan Chattopadhyay; IEEE Electron Device Kolkata Conference (EDKCON), 2018, Organized by IEEE EDS - Kolkata Chapter.
“Investigation of Process Induced Stress in the Channel of a SiGe Embedded Source/Drain Ge-FinFET Architecture”, Kunal Sinha, Hafizur Rahaman, Sanatan Chattopadhyay; IEEE International Symposium on Devices, Circuits and Systems (ISDCS), 2018, Organized by Indian Institute of Engineering Science and Technology – Shibpur, Howrah, India and Hiroshima University, Japan.
“Investigation of the Impact of Embedded SiGe Source/Drain Induced Uniaxial Stress on the Performance of Si p-channel 3D FinFETs”, Kunal Sinha, Hafizur Rahaman, Sanatan Chattopadhyay; 6th International Conference on Computers and Devices for Communication (CODEC), 2015, Organized by Institute of Radio Physics and Electronics, University of Calcutta, Calcutta, India.
“Three Dimensional Process Induced Stress in Nano-scale MOSFET using Embedded Source/Drain Technology”, Kunal Sinha, International Conference on Advanced Materials and Energy Technology (ICAMET), 2014, Organized by Indian Institute of Engineering Science and Technology – Shibpur, Howrah, India and Southern University, Baton Rouge, Louisiana, USA.
“A study on the performance of stress induced p-channel MOSFETs with embedded Si1− xGex source/drain”, Kunal Sinha, Hafizur Rahaman, Sanatan Chattopadhyay; 5th International Conference on Computers and Devices for Communication (CODEC), 2012, Organized by Institute of Radio Physics and Electronics, University of Calcutta, Calcutta, India.
“Strained Silicon – A Gateway To A Faster World”, Kunal Sinha, Hafizur Rahaman, Sanatan Chattopadhyay; National Conference on Advancement in Frontier Physics: From 20th century to the Present, 2016, Organized by Bhairab Ganguly College, Belgharia, Calcutta, India.
“A Study on the Performance of Strained Channel Dual Source Field Effect Transistor for Bio-Sensing Application”, Kunal Sinha, Sanatan Chattopadhyay, Hafizur Rahaman, Two Days National Conference on Advances in Interdisciplinary Sciences, 2017, Bhairab Ganguly College, Belgharia, Calcutta, India.
Editorial Board Membership :
Name of Journal : Americal Journal of Nanoscience (AJN)
ISSN: 2575-484X (Print)
ISSN: 2575-4858 (Online)
Website : http://www.sciencepublishinggroup.com/j/ajn
Publisher : Science Publishing Group.
548 Fashion Avenue. New York. NY 10018. USA.
Name of Journal : Electronics Science Technology and Application (ESTA)
ISSN: 2251-2608 (Print)
ISSN: 2424-8460 (Online)
Website : http://esta.usp-pl.com/index.php/esta/index
Publisher : Universe Scientific Publishing Pte Ltd
7030 Ang Mo Kio Avenue 5#04-15, Northstar@AMK. Singapore 569880.