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Hafizur Rahaman

About


Hafizur Rahaman received his B.E. (Electrical Engineering) from Calcutta University (B. E. College, Shibpur), M.E. (Electrical Engineering) and PhD (Computer Science and Engineering) degrees from the Jadavpur University, Calcutta, India in 1986, 1988 and 2003 respectively.  Dr. Rahaman is full professor of Indian Institute of Engineering Science and Technology (IIEST), Shibpur, India. Prior to joining the IIEST Shibpur, he served as Design Engineer (System) in CMPDI (GoI R & D organization).

Dr. Rahaman visited as Post Doctoral Research Fellow under EPSARC Grant in the Design and Verification Division of Computer Science Department, Bristol University, UK during 2006-2007. During 2008-2009, Dr. Rahaman received Royal Society International Fellowship award to carry out one year advanced research in the Design and Verification Division of Computer Science Department, University of Bristol, United Kingdom. He served as visiting professor at the Computer Architecture Division, University of Germany, under DST-DAAD research fellowship award during 2013-2015.

His research interests include Logic Synthesis, design and testing of Integrated Circuits and nano-biochips, Nanoscale Technologies and Computing viz. Memristors and Reversible Quantum Circuit Synthesis etc.

He leads the VLSI design and test group, Chip-to Systems Program, GoI for fabrication of integrated circuits at IIEST, Shibpur, India,

To his credit, he has supervised 24 doctoral and forty six masters’ theses besides guiding several projects at undergraduate level. Eight more doctoral theses are now in progress.

He is also active in international collaborative research with the Bristol University (UK), University of Bremen (Germany), Duke University (USA), and Hiroshima University (Japan). He has established a strong collaboration with HiSim Laboratory, Hiroshima University since 2015. Currently he is engaged in several collaborative research projects with the different companies and research organizations including ARM, Sankalp Semiconductor.

His research has been funded by DEITY (MCIT, GoI), DST (GoI), CSIR (GoI), DIT (Gov. of WB), AICTE, UGC, Royal Society-UK, DAAD Foundation (Germany) and several industrial partners. He has contributed more than 300 research articles in archival journals and refereed conference proceedings.  He has also contributed towards several book chapters in edited volumes from different publishers including CRC press, and Springer-Verlag Berlin Heidelberg etc. He published a book on emerging technology entitled “Carbon Nanotube and Graphene Nanoribbon Interconnects”, CRC Press (Taylor and Francies Group), USA, December 2014.


Dr. Rahaman is a Member of the VLSI Society of India (VSI), Senior Member of the IEEE, and ACM Sigda. He is regular reviewer of IEEE TCAD, IEEE TVLSI, IEEE TC, and ACM TODAEs.  He has served/is serving as General Chair/Program Chair/Track Chair/TPC member in several conference committees including VLSI Design, VDAT, ATS, ISED, ISVLSI, ASP-DAC, ISPD, ISDCS etc.

He has initiated an IEEE International symposium on Devices, Circuits and systems (ISDCS) in collaboration with Hiroshima University, Japan under the bi-lateral cooperation between India and Japan. This symposium will be held annually in India and in Japan alternatively. This symposium will strengthen the cooperation between the two countries.

Academic Qualifications


  • Post Doctoral [2006-07], University of Bristol, United Kingdom, EPSRC Fellowship, UK 
  • Post Doctoral [2008-2009], University of Bristol, United Kingdom, Royal Society Fellowship, UK 
  • Ph.D.(Engg.) :Computer Science and Engineering, Jadavpur University, Kolkata 
  • M.E. (Electrical Engg.) Jadavpur University, Kolkata 
  • B.E. (Electrical Engg.) B.E.College, Shibpur (Calcutta University) 

 

Research Statement


  • Logic Synthesis
  • Design & Test of VLSI Circuits
  • SOC Testing
  • Design & Testing of Micro fluidic Bio Chip
  • Nanoscale Technologies and Computing viz. Memristors and Reversible Quantum Technology based  Circuit Synthesis etc.
  • CNT/GNR based devices, circuits and interconnects

 

Latest Publications


  • 1 Monika Kumari, Niraj Kumar Singh,Manodipan Sahoo and Hafizur Rahaman, 3. Monika Kumari, Niraj Kumar 2-D Analytical Modeling and Simulation of Dual Material, Double Gate, Gate Stack Engineered, Junctionless MOSFET based Biosensor with Enhanced Sensitivity, 1-12, Silicon, 2021
  • 2 Pampa Howladar, Pranab Roy, and Hafizur Rahaman, Droplet Transportation in MEDA Based Biochips: An Enhanced Technique for Intelligent Cross Contamination Contamination Avoidance, Vol.29(7), pp.1451-1464, IEEE Transactions on Very Large Scale Integration Systems, 2021
  • 3 Pampa Howladar, Pranab Roy, and Hafizur Rahaman, MEDA Based Biochips: Detection, Prevention and Rectification Techniques for Cyberphysical Attacks, 1-12, IEEE/ACM Transactions on Computational Biology and Bioinformatics, 2021
  • 4 Monika Kumari, Niraj Kumar Singh, Manodipan Sahoo and Hafizur Rahman, Work function optimization for Enhancement of sensitivity of Dual Material(DM), Double gate(DG), Junctionless MOSFET based biosensor, 127:130, 1-86, Applied Physics A (Springer), 2021
  • 5 Abhishek Kar, M. Miura-Mattausch, M. Sengupta, H. Kikuchihara, D. Navarro, T. Iizuka, Hafizur Rahaman, and H. J. Mattausch, Simulation-Based Power-Loss Optimization of General Purpose High-Voltage SiC MOSFET Circuit under High-Frequency Operation, Vol. (9), pp: 23786 -23794, IEEE Access, 2021
  • 6 Supriyo Srimani, Manas Parai, Kasturi Ghosh and Hafizur Rahaman, A Statistical Approach of Analog Circuit Fault Detection Utilizing Kolmogorov-Smirnov Test Method, vol.(40), pp. 2091–2113, Circuits, Systems & Signal Processing (CSSP) (Springer), 2021
  • 7 Sayan Kanungo, Budhaditya Majumdar, Subhas Mukhopadhyay, Debapriya Som, Sanatan Chattopadhyay and Hafizur Rahaman, Investigation on the Effects of Substrate, Back-Gate Bias and Front-Gate Engineering on the Performance of DMTFET based Biosensors, Vol. 20(18), pp.10405-10414, IEEE Sensors Journal, 2020
  • 8 Pampa Howladar, Pranab Roy, and Hafizur Rahaman, Chip Level Design in MEDA Based Biochips: Application of Daisy Chain Based Actuation, Vol. (26), pp. 2337–2351, Microsystems Technologies (Springer Nature), 2020
  • 9 Supriyo Srimani, Manas Parai, Kasturi Ghosh and Hafizur Rahaman, A Statistical Approach of Analog Circuit Fault Detection Utilizing Kolmogorov-Smirnov Test Method, 39(4), 4281-8296, Circuits, Systems & Signal Processing (CSSP) (Springer), 2020
  • 10 Manas Parai, Supriyo Srimani, Kasturi Ghosh, and Hafizur Rahaman, Analog Circuit Fault Detection by Impulse Response Based Signature Analysis, Vol. 39, pp.4281–4296, Circuits, Systems, and Signal Processing (Springer), 2020
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    Research Areas


    • Memristor and Quantum Technology based Circuit Synthesis
    • CNT/GNR based devices, circuits and interconnects
    • Emerging Devices and Circuits
    • Design & Testing of Micro fluidic Bio Chip
    • Design & Test of VLSI Circuits
    • Logic Synthesis

    Publications


    1 Monika Kumari, Niraj Kumar Singh,Manodipan Sahoo and Hafizur Rahaman, 3. Monika Kumari, Niraj Kumar 2-D Analytical Modeling and Simulation of Dual Material, Double Gate, Gate Stack Engineered, Junctionless MOSFET based Biosensor with Enhanced Sensitivity, 1-12, Silicon, 2021 2 Pampa Howladar, Pranab Roy, and Hafizur Rahaman, Droplet Transportation in MEDA Based Biochips: An Enhanced Technique for Intelligent Cross Contamination Contamination Avoidance, Vol.29(7), pp.1451-1464, IEEE Transactions on Very Large Scale Integration Systems, 2021 3 Pampa Howladar, Pranab Roy, and Hafizur Rahaman, MEDA Based Biochips: Detection, Prevention and Rectification Techniques for Cyberphysical Attacks, 1-12, IEEE/ACM Transactions on Computational Biology and Bioinformatics, 2021 4 Monika Kumari, Niraj Kumar Singh, Manodipan Sahoo and Hafizur Rahman, Work function optimization for Enhancement of sensitivity of Dual Material(DM), Double gate(DG), Junctionless MOSFET based biosensor, 127:130, 1-86, Applied Physics A (Springer), 2021 5 Abhishek Kar, M. Miura-Mattausch, M. Sengupta, H. Kikuchihara, D. Navarro, T. Iizuka, Hafizur Rahaman, and H. J. Mattausch, Simulation-Based Power-Loss Optimization of General Purpose High-Voltage SiC MOSFET Circuit under High-Frequency Operation, Vol. (9), pp: 23786 -23794, IEEE Access, 2021
  • 6 Supriyo Srimani, Manas Parai, Kasturi Ghosh and Hafizur Rahaman, A Statistical Approach of Analog Circuit Fault Detection Utilizing Kolmogorov-Smirnov Test Method, vol.(40), pp. 2091–2113, Circuits, Systems & Signal Processing (CSSP) (Springer), 2021
  • 7 Sayan Kanungo, Budhaditya Majumdar, Subhas Mukhopadhyay, Debapriya Som, Sanatan Chattopadhyay and Hafizur Rahaman, Investigation on the Effects of Substrate, Back-Gate Bias and Front-Gate Engineering on the Performance of DMTFET based Biosensors, Vol. 20(18), pp.10405-10414, IEEE Sensors Journal, 2020 8 Pampa Howladar, Pranab Roy, and Hafizur Rahaman, Chip Level Design in MEDA Based Biochips: Application of Daisy Chain Based Actuation, Vol. (26), pp. 2337–2351, Microsystems Technologies (Springer Nature), 2020 9 Supriyo Srimani, Manas Parai, Kasturi Ghosh and Hafizur Rahaman, A Statistical Approach of Analog Circuit Fault Detection Utilizing Kolmogorov-Smirnov Test Method, 39(4), 4281-8296, Circuits, Systems & Signal Processing (CSSP) (Springer), 2020 10 Manas Parai, Supriyo Srimani, Kasturi Ghosh, and Hafizur Rahaman, Analog Circuit Fault Detection by Impulse Response Based Signature Analysis, Vol. 39, pp.4281–4296, Circuits, Systems, and Signal Processing (Springer), 2020 11 Malay Kule, Hafizur Rahaman, and Bhargab B.Bhattacharya, Function-Mapping on Defective Nano-Crossbars with Enhanced Reliability, Malay Kule, Hafizur Rahaman, and Bhargab B.Bhattacharya, "Function-Mapping on Defective Nano-Crossbars with Enhanced Reliability", Vol. 19, pp.555–564, Journal of Computational Electronics (Springer), 2020 12 Laxmidhar Biswal, Debjyoti Bhattacharjee, Anupam Chattopadhyay and Hafizur Rahaman, Techniques for fault-tolerant decomposition of multicontrolled Toffoli gates, Vol. 100, 062326, 062326, Physical Review A, 2019 13 Subhajit Das, Sandip Bhattacharya, Debaprasad Das, and Hafizur Rahaman, Modeling and Analysis of Electro-thermal Impact of Crosstalk Induced Gate Oxide Reliability in Pristine and Intercalation Doped MLGNR Interconnects, Vol. 19(3), pp. 543-550, IEEE Transactions on Device and Materials Reliability, 2019
  • 14 L. Banerjee, A Sengupta, and Hafizur Rahaman, Carrier transport and thermoelectric properties of differently shaped Germanene (Ge) and Silicene (Si) nanoribbon interconnects, Vol.66 (1), pp.664-669, IEEE Transactions on Electron Devices, 2019
  • 15 Pampa Howladar, Pranab Roy, and Hafizur Rahaman, A High-Performance Homogeneous Droplet Routing Technique for MEDA Based Biochips, 15 (4), pp. 1-37, ACM Journal on Emerging Technologies in Computing Systems, 2019
  • 16 Kasturi Ghosh, Niladri S. Mahapatra, Hafizur Rahaman and Partha Bhattacharyya, Prediction of Adsorption Probability of Oxidizing and Reducing Species on 2D Hybrid Junction of rGO-ZnO from First Principle Analysis, vol. 18(1), pp. 119-125, IEEE Transactions on Nanotechnology 2019,, 2019
  • 17 Arnab Mukherjee, Tapas K. Maiti, H.Rahaman, 1. rnab Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs, Vol.E102-C (6), pp.487-494, IEICE Transactions on Electronics, 2019
  • 18 Sabir Ali Mondal, Pradip Mondal and Hafizur Rahaman, 1. Sabir Ali Mondal, Pradip MondFast Locking, Startup Circuit Free, Low Area, 32-phase Analog DLL, Vol. (66), pp. 60-66, Integration, the VLSI Journal, (Elsevier), 2019
  • 19 Anindita Chakraborty,Vivek Saurabh,Partha Sarathi Gupta,Rituraj Kumar,Saikat Majumdar,Smriti Das and Hafizur Rahaman, In-Memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC), Vol (66), pp. 24-34, Integration, the VLSI Journal, (Elsevier), 2019
  • 20 Mukhopadhyay, A. and Maiti, T.K. and Bhattacharya, S. and Iizuka, T. and Kikuchihara, H. and Miura-Mattausch, M. and Rahaman, H. and Yoshitomi, S. and Navarro, D. and Mattausch, H.J., Prevention of highly power-efficient circuits due to short-channel effects in MOSFETs, E102C, 487-494, IEICE Transactions on Electronics, 2019
  • 21 Ghosh, K. and Mahapatra, N.S. and Rahaman, H. and Bhattacharyya, P., Prediction of adsorption probability of oxidizing and reducing species on 2-D hybrid junction of rGO-ZnO from first principle analysis, 18, 119-125, IEEE Transactions on Nanotechnology, 2019
  • 22 Chakraborty, A. and Saurabh, V. and Gupta, P.S. and Kumar, R. and Majumdar, S. and Das, S. and Rahaman, H., In-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC), 66, 24-34, Integration, 2019
  • 23 Mondal, S.A. and Mandal, P. and Rahaman, H., Fast locking, startup-circuit free, low area, 32-phase analog DLL, 66, 60-66, Integration, 2019
  • 24 Bardhan, S. and Sahoo, M. and Rahaman, H., Empirical Drain Current Model of Graphene Field-Effect Transistor for Application as a Circuit Simulation Tool, IETE Journal of Research, 2019
  • 25 Bandyopadhyay, C. and Das, R. and Chattopadhyay, A. and Rahaman, H., Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures, 13, 38-48, IET Computers and Digital Techniques, 2019
  • 26 Das, S. and Bhattacharya, S. and Das, D. and Rahaman, H., Comparative stability analysis of pristine and asf5 intercalation doped top contact graphene nano ribbon interconnects, 2019 2nd International Symposium on Devices, Circuits and Systems, ISDCS 2019 - Proceedings, 2019
  • 27 Banerjee, L. and Sengupta, A. and Rahaman, H., Carrier Transport and Thermoelectric Properties of Differently Shaped Germanene (Ge) and Silicene (Si) Nanoribbon Interconnects, 66, 664-669, IEEE Transactions on Electron Devices, 2019
  • 28 Mondal, J. and Mondal, B. and Kole, D.K. and Rahaman, H. and Das, D.K., Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits, Journal of Circuits, Systems and Computers, 2019
  • 29 Bardhan, S. and Sahoo, M. and Rahaman, H., Boltzmann transport equation-based semi-classical drain current model for bilayer GFET including scattering effects, 13, 421-427, IET Circuits, Devices and Systems, 2019
  • 30 Mondal, B. and Bandyopadhyay, C. and Bhattacharjee, A. and Rahaman, H., An Online Testing Scheme for Detection of Gate Faults in ESOP-Based Reversible Circuit, Journal of The Institution of Engineers (India): Series B, 2019
  • 31 Sinharay, A. and Das, S. and Roy, P. and Rahaman, H., An Angular Steiner Tree Based Global Routing Algorithm for Graphene Nanoribbon Circuit, 892, 670-681, Communications in Computer and Information Science, 2019
  • 32 Sharma, B. and Mukhopadhyay, A. and Banerjee, L. and Sengupta, A. and Rahaman, H. and Sarkar, C.K., Ab initio study of mono-layer 2-D insulators (X-(OH)2 and h-BN) and their use in MTJ memory device, 25, 1909-1917, Microsystem Technologies, 2019
  • 33 Bhattacharya, R. and Roy, P. and Rahaman, H., A complete routing simulator for digital microfluidic biochip, 10, 70-85, International Journal of Information System Modeling and Design, 2019
  • 34 Bardhan, S. and Sahoo, M. and Rahaman, H., A Surface Potential-Based Model for Dual Gate Bilayer Graphene Field Effect Transistor Including the Capacitive Effects, Journal of Circuits, Systems and Computers, 2019
  • 35 Bhattacharjee, A. and Bandyopadhyay, C. and Biswal, L. and Rahaman, H., A Heuristic Qubit Placement Strategy for Nearest Neighbor Realization in 2D Architecture, 892, 593-605, Communications in Computer and Information Science, 2019
  • 36 L. Banerjee, A Sengupta, and H. Rahaman, Carrier transport and thermoelectric properties of differently shaped Germanene (Ge) and Silicene (Si) nanoribbon interconnects, 66 (1), 664-669, IEEE Transactions on Electron Devices, 2019
  • 37 Sudip Poddar, Robert Wille, Hafizur Rahaman and Bhargab B. Bhattacharya, Error-Oblivious Sample Preparation with Digital Microfluidic Lab-on-Chip, Vol. 38(10), pp.1886 - 1899, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018
  • 38 Sandip Bhattacharya, Subhajit Das, Arnab Mukhopadhyay, Debaprasad Das and Hafizur Rahaman, Analysis of a temperature-dependent delay optimization model for GNR interconnects using a wire sizing method, Vol. 17(4), pp 1536–1548, Journal of Computational Electronics (Elsevier), 2018
  • 39 Subhajit Das, Debaprasad Das, and Hafizur Rahaman, Electro-thermal RF Modeling and Performance Analysis of Graphene Nanoribbon Interconnects, Vol. 17, pp. 1695–1708, Journal of Computational Electronics (Springer), 2018 40 Laxmidhar Biswal,Rakesh Das, Chandan Bandyopadhyay,Anupam Chattopadhyay and Hafizur Rahaman, A Template-based Technique for Efficient Clifford+T-based Quantum Circuit Implementation, Vol. 81, pp.58-68, Microelectronics Journal (Elsevier), 2018
  • 41 Chandan Bandyopadhyay, Rakesh Das, Robert Wille, Rolf Drechsler and Hafizur Rahaman, Synthesis of Circuits based on All-Optical Mach-Zehnder Interferometers Using Binary Decision Diagrams, VOL. 71, pp. 19-29, Microelectronics Journal(Elsevier), 2018
  • 42 Rupam Bhattacharya, Pranab Roy and Hafizur Rahaman, Homogeneous Droplet Routing In DMFB: An Enhanced Technique For High Performance Bioassay Implementation, Vol. 60, pp.74-91, Integration, the VLSI Journal, (Elsevier), 2018
  • 43 Kule, M. and Rahaman, H. and Bhattacharya, B.B., Maximal Defect-Free Component in Nanoscale Crossbar Circuits Amidst Stuck-Open and Stuck-Closed Faults, Journal of Circuits, Systems and Computers, 2018
  • 44 Bhattacharya, S. and Das, D. and Rahaman, H., Analysis of delay fault in GNR power interconnects, 31, International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 2018
  • 45 Bhattacharya, S. and Das, D. and Rahaman, H., Analysis of Simultaneous Switching Noise and IR-Drop in Side-Contact Multilayer Graphene Nanoribbon Power Distribution Network, 27, Journal of Circuits, Systems and Computers, 2018
  • 46 Bandyopadhyay, C. and Das, R. and Wille, R. and Drechsler, R. and Rahaman, H., Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams, 71, 19-29, Microelectronics Journal, 2018
  • 47 Maity, I. and Ghosh, K. and Rahaman, H. and Bhattacharyya, P., Spin Dependent Electronic Transport in Edge Oxidized Zigzag Graphene Nanoribbon, 5, 9892-9898, Materials Today: Proceedings, 2018
  • 48 Bandyopadhyay, C. and Parekh, S. and Rahaman, H., Improved circuit synthesis approach for exclusive-sum-of-product-based reversible circuits, 12, 167-175, IET Computers and Digital Techniques, 2018
  • 49 Bhattacharya, R. and Roy, P. and Rahaman, H., Homogeneous droplet routing in DMFB: An enhanced technique for high performance bioassay implementation, 60, 74-91, Integration, the VLSI Journal, 2018
  • 50 Hazra, S. and Ghosh, S. and De, S. and Rahaman, H., FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time, 14, 193-221, Journal of Real-Time Image Processing, 2018
  • 51 Poddar, S. and Wille, R. and Rahaman, H. and Bhattacharya, B.B., Error-Oblivious Sample Preparation with Digital Microfluidic Lab-on-Chip, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018
  • 52 Das, S. and Das, D. and Rahaman, H., Electro-thermal RF modeling and performance analysis of graphene nanoribbon interconnects, 17, 1695-1708, Journal of Computational Electronics, 2018
  • 53 Howladar, P. and Roy, P. and Rahaman, H., Design Automation and Testing of MEDA-Based Digital Microfluidic Biochips: A Brief Survey, IETE Journal of Research, 2018
  • 54 Bhattacharya, S. and Das, S. and Mukhopadhyay, A. and Das, D. and Rahaman, H., Analysis of a temperature-dependent delay optimization model for GNR interconnects using a wire sizing method, 17, 1536-1548, Journal of Computational Electronics, 2018
  • 55 Biswal, L. and Das, R. and Bandyopadhyay, C. and Chattopadhyay, A. and Rahaman, H., A template-based technique for efficient Clifford+T-based quantum circuit implementation, 81, 58-68, Microelectronics Journal, 2018
  • 56 Sudip Poddar, Robert Wille, Hafizur Rahaman and Bhargab B. Bhattacharya, Error-Oblivious Sample Preparation with Digital Microfluidic Lab-on-Chip, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018 57 Laxmidhar Biswal,Rakesh Das, Chandan Bandyopadhyay,Anupam Chattopadhyay and Hafizur Rahaman, A Template-based Technique for Efficient Clifford+T-based Quantum Circuit Implementation, 81 (2018), 58-68, Microelectronics Journal (Elsevier), 2018 58 Subhajit Das, Debaprasad Das, and Hafizur Rahaman, Electro-thermal RF Modeling and Performance Analysis of Graphene Nanoribbon Interconnects, Journal of Computational Electronics (Springer), 2018 59 Sandip Bhattacharya,Subhajit Das, Arnab Mukhopadhyay, Debaprasad Das, and Hafizur Rahaman, Analysis of Temperature Dependent Delay Optimization Model for GNR Interconnect Using Wire Sizing Method, Journal of Computational Electronics (Springer), 2018 60 Anindita Chakraborty,Vivek Saurabh,Partha Sarathi Gupta,Rituraj Kumar,Saikat Majumdar,Smriti Das and Hafizur Rahaman, In-Memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC), Integration, the VLSI Journal, (Elsevier), 2018
  • 61 Sayan Kanunga, Sabir Ali Mondal, Sanatan Chottopadhyaya and Hafizur Rahaman, Design and Investigation on Bio-Inverter and Bio-Ring-oscillator for Dielectrically Modulated Bio-sensing Applications, Vol. 16(6), pp. 974 – 981, IEEE Transactions on Nanotechnology, 2017
  • 62 Sayan Kanungo, Sanatan Chattopadhyay, Kunal Sinha, Partha Sarathi Gupta, and Hafizur Rahaman, A Device Simulation-Based Investigation on Dielectrically Modulated Fringing Field-Effect Transistor for Biosensing Applications, Vol.17(5), pp.1399-1406, IEEE Sensors Journal, 2017
  • 63 Kasturi Ghosh, Hafizur Rahaman and Partha Bhattacharyya, Potentiality of Density-Functional Theory in Analyzing the Devices Containing Graphene - Crystalline Solid Interfaces, Vol.64 (11), pp.4738-4745, IEEE Transactions on Electron Devices, 2017
  • 64 Kunal Sinha, Sanatan Chattopadhyay, Partha Sarathi Gupta and Hafizur Rahaman, A Technique to incorporate both tensile and compressive channel stress in Ge FinFET architecture, Volume 16 (3), pp 620–630, Journal of Computational Electronics (Springer), 2017
  • 65 Supriyo Srimani, Kasturi Ghosh, and Hafizur Rahaman, Parametric Fault Detection of Analog Circuits based on Bhattacharyya Measure, Vol.93(3), pp 477–488, Analog Integrated Circuits and Signal Processing (Springer), 2017
  • 66 Tiwari, S. and Dolai, S. and Rahaman, H. and Gupta, P.S., Effect of temperature and phonon scattering on the drain current of a MOSFET using SL-MoS as its channel material, 463, 108-117, Journal of Non-Crystalline Solids, 2017
  • 67 Adak, S. and Swain, S.K. and Pardeshi, H. and Rahaman, H. and Sarkar, C.K., Effect of barrier thickness on linearity of underlap AlInN/GaN DG-MOSHEMTs, 12, Nano, 2017
  • 68 Kanungo, S. and Mondal, S.A. and Chattopadhyay, S. and Rahaman, H., Design and Investigation on Bioinverter and Bioring-Oscillator for Dielectrically Modulated Biosensing Applications, 16, 974-981, IEEE Transactions on Nanotechnology, 2017
  • 69 Das, D. and Rahaman, H., Carbon nanotube and graphene nanoribbon interconnects, 1-168, Carbon Nanotube and Graphene Nanoribbon Interconnects, 2017
  • 70 Sahoo, M. and Rahaman, H., Analysis of Crosstalk-Induced Effects in Multilayer Graphene Nanoribbon Interconnects, 26, Journal of Circuits, Systems and Computers, 2017
  • 71 Sinha, K. and Chattopadhyay, S. and Gupta, P.S. and Rahaman, H., A technique to incorporate both tensile and compressive channel stress in Ge FinFET architecture, 16, 620-630, Journal of Computational Electronics, 2017
  • 72 Maity, I. and Ghosh, K. and Rahaman, H. and Bhattacharyya, P., Tuning of electronic properties of edge oxidized armchair graphene nanoribbon by the variation of oxygen amounts and positions, 28, 9039-9047, Journal of Materials Science: Materials in Electronics, 2017
  • 73 Bhattacharya, S. and Das, D. and Rahaman, H., Stability Analysis in Top-Contact and Side-Contact Graphene Nanoribbon Interconnects, 63, 588-596, IETE Journal of Research, 2017
  • 74 Maity, I. and Ghosh, K. and Rahaman, H. and Bhattacharyya, P., Selectivity Tuning of Graphene Oxide Based Reliable Gas Sensor Devices by Tailoring the Oxygen Functional Groups: A DFT Study Based Approach, 17, 738-745, IEEE Transactions on Device and Materials Reliability, 2017
  • 75 Ghosh, K. and Rahaman, H. and Bhattacharyya, P., Potentiality of Density-Functional Theory in Analyzing the Devices Containing Graphene-Crystalline Solid Interfaces: A Review, 64, 4738-4745, IEEE Transactions on Electron Devices, 2017
  • 76 Srimani, S. and Parai, M.K. and Ghosh, K. and Rahaman, H., Parametric fault detection of analog circuits based on Bhattacharyya measure, 93, 477-488, Analog Integrated Circuits and Signal Processing, 2017
  • 77 Bhattacharya, S. and Das, D. and Rahaman, H., Modeling and Performance Analysis of Graphene Nanoribbon Interconnects, 40, 325-329, National Academy Science Letters, 2017
  • 78 Tiwari, S. and Dolai, S. and Rahaman, H. and Gupta, P.S., Effect of temperature and phonon scattering on the drain current of a MOSFET using SL-MoS as its channel material, 111, 912-921, Superlattices and Microstructures, 2017
  • 79 Kanungo, S. and Chattopadhyay, S. and Sinha, K. and Gupta, P.S. and Rahaman, H., A Device Simulation-Based Investigation on Dielectrically Modulated Fringing Field-Effect Transistor for Biosensing Applications, 17, 1399-1406, IEEE Sensors Journal, 2017
  • 80 Sayan Kanungo, Sanatan Chattopadhyay, Kunal Sinha, Partha Sarathi Gupta, and Hafizur Rahaman, A Device Simulation-Based Investigation on Dielectrically Modulated Fringing Field-Effect Transistor for Biosensing Applications, 17(5), 1399-1406, IEEE Sensors Journal, 2017
  • 81 Sayan Kanunga, Sabir Ali Mondal, Sanatan Chottopadhyaya and Hafizur Rahaman, Design and Investigation on Bio-Inverter and Bio-Ring-oscillator for Dielectrically Modulated Bio-sensing Applications, 16(6), 974 – 981, IEEE Transactions on Nanotechnology, 2017
  • 82 Supriyo Srimani, Kasturi Ghosh, and Hafizur Rahaman, Parametric Fault Detection of Analog Circuits based on Bhattacharyya Measure, 93(3), 477–488, Analog Integrated Circuits and Signal Processing (Springer), 2017
  • 83 Partha Sarathi Gupta, Hafizur Rahaman, Kunal Sinha, and Sanatan Chattopadhyay, An Optoelectronic Band-to-band Tunnel Transistor for Near-infrared Sensing Applications: Device Physics, Modeling, and Simulation, Vol. 120, 084510, Journal of Applied Physics (AIP Publishing), 2016
  • 84 Sayan Kanungo, Sanatan Chattopadhyay, Partha Sarathi Gupta, Kunal Sinha and Hafizur Rahaman, Study and Analysis of the Effects of SiGe Source and Pocket Doped Channel on Sensing Performance of Dielectrically-Modulated Tunnel FET based Bio-Sensors, Volume 63(6), pp.2589 - 2596, IEEE Transactions on Electron Devices, 2016
  • 85 Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya, Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability, Volume 12(4), Article No.:34, ACM Journal on Emerging Technologies in Computing Systems (JETC), 2016 86 Pranab Roy, Swati Saha, and Hafizur Rahaman, Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips, Vol.25(11), pp-3345 - 3358, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
  • 87 Soumyajit Poddar, Prasun Ghosal, and Hafizur Rahaman, Design of a High Performance CDMA Based Broadcast Free Photonic Multi Core Network on Chip, Vol. 15(1), Article No.(2), ACM Transactions on Embedded Computing Systems, 2016
  • 88 L. Banerjee, A Mukhopadhyay, A Sengupta, and H. Rahaman, Performance analysis of uniaxially strained monolayer black phosphorus and blue phosphorus n-MOSFET and p-MOSFET, Vol. 15 (3), pp.919-930, Journal of Computational Electronics (Springer), 2016
  • 89 Ananda Sankar Chakraborty, Sabir Ali Mondal and Hafizur Rahaman, Low Noise and Low Power Switched Biased CSA with Clocked Reset and Minimal PVT Variation for APD Based Positron Emission Tomography, Vol. 88, pp.495–504, Journal of Analog Integrated Circuits and Signal Processing (Springer), 2016
  • 90 Manodipan Sahoo and Hafizur Rahaman, Modeling and Analysis of Crosstalk Induced Overshoot/Undershoot Effects in Multilayer Graphene Nanoribbon Interconnects and Its Impact on Gate Oxide Reliability, Vol. 63, pp.231-238, Microelectronics Reliability (Elsevier), 2016
  • 91 Sandip Bhattacharya, Debaprasad Das and Hafizur Rahaman, Reduced Thickness Interconnect Model using GNR to Avoid Crosstalk Effects, Vol. 15(2), pp..367–380, Journal of Computational Electronics (JCEL) (Springer), 2016
  • 92 Roy, P. and Saha, S. and Rahaman, H., Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips, 24, 3345-3358, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
  • 93 Bhattacharya, S. and Das, D. and Rahaman, H., Temperature dependent IR-drop analysis in graphene nanoribbon based power interconnect, 8, Journal of Nano- and Electronic Physics, 2016
  • 94 Kanungo, S. and Chattopadhyay, S. and Gupta, P.S. and Sinha, K. and Rahaman, H., Study and Analysis of the Effects of SiGe Source and Pocket-Doped Channel on Sensing Performance of Dielectrically Modulated Tunnel FET-Based Biosensors, 63, 2589-2596, IEEE Transactions on Electron Devices, 2016
  • 95 Deb, A. and Das, D.K. and Rahaman, H. and Wille, R. and Drechsler, R. and Bhattacharya, B.B., Reversible synthesis of symmetric functions with a simple regular structure and easy testability, 12, ACM Journal on Emerging Technologies in Computing Systems, 2016
  • 96 Bhattacharya, S. and Das, D. and Rahaman, H., Reduced thickness interconnect model using GNR to avoid crosstalk effects, 15, 367-380, Journal of Computational Electronics, 2016
  • 97 Banerjee, L. and Mukhopadhyay, A. and Sengupta, A. and Rahaman, H., Performance analysis of uniaxially strained monolayer black phosphorus and blue phosphorus n-MOSFET and p-MOSFET, 15, 919-930, Journal of Computational Electronics, 2016
  • 98 Roy, S.K. and Giri, C. and Rahaman, H., Optimization of Test Wrapper for TSV Based 3D SOCs, 32, 511-529, Journal of Electronic Testing: Theory and Applications (JETTA), 2016
  • 99 Sahoo, M. and Rahaman, H., Modeling and analysis of crosstalk induced overshoot/undershoot effects in multilayer graphene nanoribbon interconnects and its impact on gate oxide reliability, 63, 231-238, Microelectronics Reliability, 2016
  • 100 Chakraborty, A.S. and Mondal, S.A. and Rahaman, H., Low noise and low power switched biased CSA with clocked reset and minimal PVT variation for APD based positron emission tomography, 88, 495-504, Analog Integrated Circuits and Signal Processing, 2016
  • 101 Sinha, K. and Gupta, P.S. and Chattopadhyay, S. and Rahaman, H., Investigating the performance of SiGe embedded dual source p-FinFET architecture, 98, 37-45, Superlattices and Microstructures, 2016
  • 102 Das, D. and Rahaman, H., Investigating the Applicability of Graphene Nanoribbon as Signal and Power Interconnects for Nanometer Designs, 25, Journal of Circuits, Systems and Computers, 2016
  • 103 Adak, S. and Swain, S.K. and Dutta, A. and Rahaman, H. and Sarkar, C.K., Influence of channel length and High-K oxide thickness on Subthreshold DC performance of graded channel and gate stack DG-MOSFETs, 11, Nano, 2016
  • 104 Adak, S. and Swain, S.K. and Rahaman, H. and Sarkar, C.K., Impact of gate engineering in enhancement mode n++GaN/InAlN/AlN/GaN HEMTs, 100, 306-314, Superlattices and Microstructures, 2016
  • 105 Poddar, S. and Ghosal, P. and Rahaman, H., Design of a high-performance cdma-based broadcast-free photonic multi-core network on chip, 15, ACM Transactions on Embedded Computing Systems, 2016
  • 106 Sharma, B. and Mukhopadhyay, A. and Sengupta, A. and Rahaman, H. and Sarkar, C.K., Analysis of tunneling currents in multilayer black phosphorous and MoS non-volatile flash memory cells, 15, 129-137, Journal of Computational Electronics, 2016
  • 107 Bhattacharya, S. and Das, D. and Rahaman, H., Analysis of temperature dependent power supply voltage drop in graphene nanoribbon and Cu based power interconnects, 3, 1493-1506, AIMS Materials Science, 2016
  • 108 Gupta, P.S. and Rahaman, H. and Sinha, K. and Chattopadhyay, S., An optoelectronic band-to-band tunnel transistor for near-infrared sensing applications: Device physics, modeling, and simulation, 120, Journal of Applied Physics, 2016
  • 109 Sayan Kanungo, Sanatan Chattopadhyay, Partha Sarathi Gupta and Hafizur Rahaman, Comparative Performance Analysis of the Dielectrically Modulated Full Gate and Short Gate Tunnel FET based Bio-Sensors, 62(3), 994 - 1001, IEEE Transactions on Electron Devices (TED 2015), 2016
  • 110 Soumyajit Poddar, Prasun Ghosal, and Hafizur Rahaman, Design of a High Performance CDMA Based Broadcast Free Photonic Multi Core Netweork on Chip, 15(1), 1-30, ACM Transactions on Embedded Computing Systems, 2016
  • 111 Sandip Bhattacharya, Debaprasad Das and Hafizur Rahaman, Reduced Thickness Interconnect Model using GNR to Avoid Crosstalk Effects, 15(2), 367–380, Journal of Computational Electronics (JCEL), 2016 112 Pranab Roy, Swati Saha, and Hafizur Rahaman, Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips, 25(11), 2245-3358, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
  • 113 Sayan Kanungo, Sanatan Chattopadhyay, Partha Sarathi Gupta, Kunal Sinha and Hafizur Rahaman, Study and Analysis of the Effects of SiGe Source and Pocket Doped Channel on Sensing Performance of Dielectrically-Modulated Tunnel FET based Bio-Sensors, 63(6), 2589 - 2596, IEEE Transactions on Electron Devices, 2016
  • 114 Manodipan Sahoo and Hafizur Rahaman, Modeling and Analysis of Crosstalk Induced Overshoot/Undershoot Effects in Multilayer Graphene Nanoribbon Interconnects and Its Impact on Gate Oxide Reliability, 63, 231-238, Microelectronics Reliability(Elsevier), 2016
  • 115 Partha Sarathi Gupta, Hafizur Rahaman, Kunal Sinha, and Sanatan Chattopadhyay, An Optoelectronic Band-to-band Tunnel Transistor for Near-infrared Sensing Applications: Device Physics, Modeling, and Simulation, 120, 084510, Journal of Applied Physics, 2016 116 Partha Sarathi Gupta, Sanatan Chattopadhyay, Partha Sarathi Dasgupta and Hafizur Rahaman, A Novel Photo-sensitive Tunneling Transistor For Near-Infrared Sensing Applications: Design, Modeling and Simulation, Vol.62(5), pp.1516-1523, IEEE Transactions on Electron Devices, 2015
  • 117 A Mukhopadhyay, L Banerjee, A Sengupta, H Rahaman, Effect of stacking order on device performance of bilayer black phosphorene-field-effect transistor, Vol. 118 (22), 224501, Journal of Applied Physics, 2015 (Springer), 2015
  • 118 Kamalika Datta, Indranil Sengupta, and Hafizur Rahaman, A Post-Synthesis Optimization Technique for Reversible Circuits Exploiting Negative Control Lines, Vol. 64(4), pp.1208-1214, IEEE Transactions on Computers, 2015
  • 119 Sayan Kanungo, Sanatan Chattopadhyay, Partha Sarathi Gupta and Hafizur Rahaman, Comparative Performance Analysis of the Dielectrically Modulated Full Gate and Short Gate Tunnel FET based Bio-Sensors, Vol.62(3), pp. 994 - 1001, IEEE Transactions on Electron Devices, 2015
  • 120 Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, and Bhargab B. Bhattacharya, Automated Washing Schemes for Residue Removal in Digital Microfluidic Biochips to Enhance Reliability, Vol. 21(1), pp. 1-17, ACM Transactions on Design Automation of Electronic Systems, 2015
  • 121 Manodipan Sahoo, Prasun Ghosal and Hafizur Rahaman, Performance Modeling and Analysis of Carbon Nanotube Bundles for Future VLSI Circuit Applications, Vol.13(3), pp.673-688, Journal of Computational Electronics (Springer), 2015
  • 122 Gupta, P.S. and Chattopadhyay, S. and Dasgupta, P. and Rahaman, H., A novel photosensitive tunneling transistor for near-infrared sensing applications: Design, modeling, and simulation, 62, 1516-1523, IEEE Transactions on Electron Devices, 2015
  • 123 Mathew, J. and Rahaman, H. and Patra, P. and Pradhan, D., Selected articles from the IEEE ISED 2014 conference, 11, 373-374, Journal of Low Power Electronics, 2015
  • 124 Roy, S.K. and Giri, C. and Rahaman, H., Optimisation of test architecture in threedimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips, 9, 268-274, IET Computers and Digital Techniques, 2015
  • 125 Mitra, D. and Ghoshal, S. and Rahaman, H. and Chakrabarty, K. and Bhattacharya, B.B., Offline washing schemes for residue removal in digital microfluidic biochips, 21, ACM Transactions on Design Automation of Electronic Systems, 2015
  • 126 Sahoo, M. and Rahaman, H., Modeling of crosstalk induced effects in copper-based nanointerconnects: An ABCD parameter matrix-based approach, 24, Journal of Circuits, Systems and Computers, 2015
  • 127 Sahoo, M. and Ghosal, P. and Rahaman, H., Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects: An ABCD Parameter-Based Approach, 14, 259-274, IEEE Transactions on Nanotechnology, 2015
  • 128 Chanak, P. and Banerjee, I. and Rahaman, H., Load management scheme for energy holes reduction in wireless sensor networks, 48, 343-357, Computers and Electrical Engineering, 2015
  • 129 Mukhopadhyay, A. and Banerjee, L. and Sengupta, A. and Rahaman, H., Effect of stacking order on device performance of bilayer black phosphorene-field-effect transistor, 118, Journal of Applied Physics, 2015
  • 130 Kanungo, S. and Chattopadhyay, S. and Gupta, P.S. and Rahaman, H., Comparative performance analysis of the dielectrically modulated full- gate and short-gate tunnel FET-based biosensors, 62, 994-1001, IEEE Transactions on Electron Devices, 2015
  • 131 Datta, K. and Sengupta, I. and Rahaman, H., A post-synthesis optimization technique for reversible circuits exploiting negative control lines, 64, 1208-1214, IEEE Transactions on Computers, 2015
  • 132 Gupta, P.S. and Chattopadhyay, S. and Dasgupta, P. and Rahaman, H., A novel photosensitive tunneling transistor for near-infrared sensing applications: Design, modeling, and simulation, 62, 1516-1523, IEEE Transactions on Electron Devices, 2015
  • 133 Debasis Mitra, Sarmishtha Ghoshal, Hafizur Rahaman, Krishnendu Chakrabarty, and Bhargab B. Bhattacharya, Automated Washing Schemes for Residue Removal in Digital Microfluidic Biochips to Enhance Reliability, 21(1), 17, ACM Transactions on Design Automation of Electronic Systems, 2015
  • 134 Manodipan Sahoo, Prasun Ghosal and, Hafizur Rahaman, Modeling and Analysis of Cross talk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects: An ABCD Parameter Based Approach, 14(2), 259 - 274, IEEE Transactions on Nanotechnology, 2015
  • 135 Kamalika Datta, Indranil Sengupta, and Hafizur Rahaman, A Post-Synthesis Optimization Technique for Reversible Circuits Exploiting Negative Control Lines, 64(4), 1208-1214, IEEE Transactions on Computers, 2015
  • 136 Partha Sarathi Gupta, Sanatan Chattopadhyay, Partha Sarathi Dasgupta and Hafizur Rahaman, A Novel Photo-sensitive Tunneling Transistor For Near-Infrared Sensing Applications: Design, Modeling and Simulation, 62(5), 1516-1523, IEEE Transactions on Electron Devices, (TED 2015), 2015
  • 137 Kamalika Datta, Gaurav Rathi, Indranil Sengupta and Hafizur Rahaman, An Improved Reversible Circuit Synthesis Approach using Clustering of ESOP Cubes, Vol. 11(2), pp. 1-15, ”, ACM Journal on Emerging Technologies in Computing Systems (JETC), 11(2):15(2014)., 2014
  • 138 Sahoo, M. and Ghosal, P. and Rahaman, H., Performance modeling and analysis of carbon nanotube bundles for future VLSI circuit applications, 13, 673-688, Journal of Computational Electronics, 2014
  • 139 Banerjee, I. and Chanak, P. and Rahaman, H. and Samanta, T., Effective fault detection and routing scheme for wireless sensor networks, 40, 291-306, Computers and Electrical Engineering, 2014
  • 140 Datta, K. and Rathi, G. and Sengupta, I. and Rahaman, H., An improved reversible circuit synthesis approach using clustering of ESOP cubes, 11, ACM Journal on Emerging Technologies in Computing Systems, 2014
  • 141 Ghosal, P. and Rahaman, H. and Mukherjee, K. and Ballabh, D., A low power, low jitter DLL based low frequency (250 kHz) clock generator, 7, 3-11, International Journal of Signal and Imaging Systems Engineering, 2014
  • 142 Manodipan Sahoo, Prasun Ghosal and Hafizur Rahaman, Performance Modeling and Analysis of Carbon Nanotube Bundles for Future VLSI Circuit Applications, 13(3), 673-688, Journal of Computational Electronics (Springer), 2014
  • 143 Kole, D.K. and Rahaman, H. and Das, D.K. and Bhattacharya, B.B., Derivation of test set for detecting multiple missing-gate faults in reversible circuits, 39, 225-236, Computers and Electrical Engineering, 2013
  • 144 Das, N. and Roy, P. and Rahaman, H., Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate arrays, 7, 210-220, IET Computers and Digital Techniques, 2013
  • 145 Das, N. and Roy, P. and Rahaman, H., Bridging fault detection in cluster based FPGA by using Muller C element, 39, 2469-2482, Computers and Electrical Engineering, 2013
  • 146 Debaprasad Das and Hafizur Rahaman, Modeling of Single-Wall Carbon Nanotube Interconnects for Different Process, Temperature, and Voltage Conditions and Investigating Timing Delay, Vol. 11(4), pp. 349-363, Journal of Computational Electronics (Springer), 2012
  • 147 Pranab Roy, Hafizur Rahaman and Parthasarthi Das Gupta, Two-level Clustering-based Techniques for Intelligent Droplet Routing in Digital Microfluidic Biochips, Vol.45 (3), pp.316-330, Integration, the VLSI Journal (Elsevier), 2012
  • 148 Debaprasad Das and Hafizur Rahaman, Modeling of Single-Wall Carbon Nanotube Interconnects for Different Process, Temperature, and Voltage Conditions and Investigating Timing Delay, 11(4), 349-363, Journal of Computational Electronics (Springer), 2012
  • 149 Debaprasad Das and Hafizur Rahaman, Crosstalk Overshoot/undershoot Analysis and its impact on Gate Oxide Reliability in Multi-wall Carbon Nanotube Interconnects, Vol. 10(4), pp..360-372, Journal of Computational Electronics (Springer), 2011
  • 150 Debaprasad Das and Hafizur Rahaman, Analysis of Crosstalk in Single- and Multi-Wall Carbon Nanotube Interconnects and its Impact on Gate Oxide Reliability, Vol. 10(6), pp. 1362-1370, IEEE Transactions on Nanotechnology, 2011
  • 151 Debaprasad Das and Hafizur Rahaman, Analysis of Crosstalk in Single- and Multi-Wall Carbon Nanotube Interconnects and its Impact on Gate Oxide Reliability, 10(6), 1362-1370, IEEE Transactions on Nanotechnology, 2011
  • 152 Debaprasad Das and Hafizur Rahaman, Crosstalk Overshoot/undershoot Analysis and its impact on Gate Oxide Reliability in Multi-wall Carbon Nanotube Interconnects, 10(4), 360-372, Journal of Computational Electronics (Springer), 2011
  • 153 Hafizur Rahaman, Jimson Mathew and Dhiraj K. Pradhan, Test Generation in Systolic Architecture for Multiplication over GF(2^m), Vol. 18(9), pp.1366-1371, IEEE Transactions on VLSI Systems, 2010
  • 154 Somsubhra Talapatra, Hafizur Rahaman, and J. Mathew, Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF(2^m), Vol.18(5), pp.847-852, IEEE Transactions on VLSI Systems, 2010
  • 155 Hafizur Rahaman, J. Mathew, A. M. Jabir and D. K. Pradhan, C-Testable Bit Parallel Multipliers over GF(2^m), Vol. 13, No. 1, Article 5, pp.1-16, ACM Transactions on Design Automation of Electronic Systems, 2008
  • 156 Hafizur Rahaman, J. Mathew, A. M. Jabir and D. K. Pradhan, Derivation of Reduced Test Vectors to Test Bit Parallel Multipliers over GF(2^m), Vol.57(9), pp.1289-1294, IEEE Transactions on Computers, 2008
  • 157 Hafizur Rahaman, D. K. Das, and B. B. Bhattacharya, An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Complex Cell, Vol. 57(12), pp.2838-2845, IEEE Transactions on Instrumentation and Measurement, 2008
  • Patents


    # Patents Year
    1 Crossover Biasing Technique for Quad Input Differential Amplifiers (Indian Patent No.196/KOL/2013A, Filed on 20-02-2013, Issued on 25-09-2015) 2015
    2 A Novel Reusable Sub Volt Differential Amplifier Module for Use as a Preamplifier Output Stage (Indian Patent No. 169/KOL/2013A, 25-09-15, Filed on 20-02-2013, Issued on 25-09-2015). 2015
    3 US Patents: Hardware accelerator for efficient convolution processing Inventors (Publication date: 2020/8/20, Application number: 16858637) 2020

    Member


    IEEE Senior Member

    IEEE Computer Society

    IEEE Circuits and Systems Society

    IEEE Test Technology Technical Council (TTTC)

    IEEE Council on Electronic Design Automation (CEDA) 

    International Steering Committee Member

    International Steering Committee Member,

    International Linkage Degree Programme (ILDP) Committee, Japan Since 2018

    Steering Committee Member

    International Steering Committee Member since 2019

    IEEE Asian Test Symposium under IEEE Computer Society

    Fellow

    Institution of Engineers (India) [IEI] 

    Fellow

    Institution of Electronics and Telecommunication Engineers

    Member

    VLSI Society of India (VSI)

    ACM Member

    ACM Sigda

    Responsibilities


    Head of Department
    10th July 2020 -

    School of VLSI Technology, IIEST Shibpur

    Head of Department
    10 July 2018 - 9th July 2020

    Department of Information Technology, IIEST Shibpur

    Chairman
    Since Januar 2019

    Committee for Committee for Central Facility for High End Software

     

    Nodal Officer, Visvesvara PhD Scheme, GoI
    Septem 2014 - January 2021

    Nodal Officer – Visvesvara PhD Scheme (7.5 Crore Project by Diety Micty,GOI) since 2014

    • Preparation and  presentation of Visvesvara PhD Scheme and maintaining activities of Visvesvara PhD Scheme (7.5 Crore Project by Diety Micty,GOI). Coordinating the research activities with Diety Micty,GOI.
    • Presenting the proposal for Visvesvaraya PhD fellowship on behalf of our institute (ETC, CST, IT and VLSI) before the Academic Committee, Media Lab., Department of Electronics and Information Technology, Ministry of Communications and Information technology, Government of India to enhance the number of PhDs in the Electronic Design and Manufacturing (ESDM) and IT/IT enabled Services (ITES) sector.
    • Sanctioning Authority                   : Diety, MCIT, Gov. of India
    • Number of Fellowship Received : 22 (For ETC, CST, IT and VLSI)
    • Year of Sanction & duration         : 2015 June and November, (Five years)
    • Amount                                            : Rs.8.50Crore
    Director-Incharge (IIIT Kalyani )
    June 2017 (One Month)

    Mentor Director was on Leave for USA

    EXecutive Director/Professor-Incharge
    2017 January - 2017 November

    Co-ordinating the day to day Academic and administrative activities of IIIT Kalyani as Mentor Institute and reporting to Mentor-Director.

    Setting up different Laboratories like Computer laboratory, Digital Design, Basic Electronics/Electrical Engineering, Microprocessor, Computer Architecture etc. at Indian Institute of Information Technology, Kalyani (IIIT-K) as mentor Institute. 

     

    Profess-Incharge
    January 2013 -December 2016

    Co-ordinating the day to day Academic and administrative activities of IIIT Kalyani as Mentor Institute and reporting to Mentor-Director

    Convener
    2014-2019

    Advisory Committee on Faculty Recruitment (ACOFAR), IIEST Shibpur

    Head of Department
    February 2015-July 2018

    School of VLSI Technology, IIEST Shibpur

    Head of Department , School of VLSI Technology, IIEST Shibpur
    February 2012 -January 2015

    Leading VLSI Activities at this Institute

    • Setting up Ganapati Sengupta VLSI Laboratory at this Institute to promote VLSI and Embedded activities in this Institute in the year 2005
    • Establishment of School of VLSI Technology to promote the research and education in the various areas of VLSI Design in our Institute in the year of 2006.
    • Coordinator - Special Manpower Development project related to VLSI design and related software (SMPD-II), sponsored by Govt. of India
    • Introduction of M-Tech (VLSI Design) during academic session 2006-2007 under SMDP-II,  a mission project of Govt. of Government of India to promote research and education in the field of VLSI Design and related area
    • Formation of   course curriculum for Master of Technology (VLSI Design) Programme
    • Setting up different VLSI Laboratories in this School
    • Introduction of EDA training programme for Academic and Industry
    • Head & Convener  Ph.D Committee, School of VLSI Technology since 1st December 2012
    Head of Department
    January 2008 - January 2012

    Department of Information Technology, IIEST Shibpur

    • Setting up different laboratories for B.E.(IT) course introduced in the year 2000 under headship
    • Preparation of list of laboratory experiments for different practical subjects for this new department
    • Revision of course curriculum for BE(IT) course in 2006/2010 under my headship
    • Introduction of Master of Engineering in Information Technology in the IT Department in the year of 2006 under my headship
    • Formation of   course curriculum for Master of Engineering in Information Technology programme
    • Vice Chairman, Board of Studies, Information Technology Department since 2008 
    • Introduction of PhD programme in the different areas of Information Technology in the year of 2006
    • Head & Convener, Ph.D Committee, Information Technology during Jan. 2005-Jan. 2012
    Head of Department
    January 2005 - January 2008

    Department of Information Technology, IIEST Shibpur

    • Setting up different laboratories for B.E.(IT) course introduced in the year 2000 under headship
    • Preparation of list of laboratory experiments for different practical subjects for this new department
    • Revision of course curriculum for BE(IT) course in 2006/2010 under my headship
    • Introduction of Master of Engineering in Information Technology in the IT Department in the year of 2006 under my headship
    • Formation of   course curriculum for Master of Engineering in Information Technology programme
    • Vice Chairman, Board of Studies, Information Technology Department since 2008
    • Introduction of PhD programme in the different areas of Information Technology in the year of 2006
    • Head & Convener, Ph.D Committee, Information Technology during Jan. 2005-Jan. 2008

    Projects


    • Device, Circuits and Architectures for implementing Probabilistic Spin Logic for Energy Efficient Boolean and Non-Boolean Computing, Sponsored
      Ongoing
    • Development of high efficiency power electronic converter technology using next generation Si/SiC-based switching devices with integrated gate drivers for high frequency operation at reduced losses, Sponsored
      Ongoing
    • Design-for-Test Solutions for 3D Integrated circuits Amount-INR 89,34,225/- Sponsoring Agency: Sparc, MHRD, GoI, Sponsored
      Ongoing
    • Design and ASIC implementation of Data Converter to be embedded with Versatile Data Acquisition and Signal Processing Platform, Sponsored
      Completed
    • Testing and Design-for-Testability for Digital Integrated Circuits (Foreign Faculty: Prof. Krishnendu Chakrabarty, IEEE/ACM Fellow, Duke University, USA Host Faculty: Prof. Hafizur Rahaman), Sponsored
      Completed
    • Charge and Spin Based Electronics: From Devices to Circuits and Systems (Foreign Faculty: Prof. Kaushik Roy, IEEE Fellow, Purdue University, USA Host Faculty: Hafizur Rahaman), Sponsored
      Completed
    • Synthesis of Reversible Circuits using Probabilistic Methods and Functional Transformations, Sponsored
      Completed
    • Design and ASIC Implementation of S-Box Circuit for Efficient Implementation of AES Algorithm, Sponsored
      Completed
    • Design and ASIC Implementation of VCO integrated with a buffer for gas sensing applications in mines and High Slew Rate High Gain Comparator for Low Phase Detection, Sponsored
      Completed
    • Design and Development of Simulation Framework on Process and Device using Synopsys TCAD, Sponsored
      Completed
    • Development of Computing Architecture in Cloud Environment, Sponsored
      Completed
    • Efficient Test infrastructure Design for 3D Multi-core Integrated Circuits, Sponsored
      Completed
    • Efficient Synthesis of Optimized Testable Hardware for Polynomials over GF(2m), Sponsored
      Completed
    • Development of FPGA Band Embedded System for Network on Chip (NOC) Application, Sponsored
      Completed
    • Fault Tolerant Routing in Wireless Sensor Networks, Sponsored
      Completed

    Awards


    • International Steering Committee Member of IEEE Asian Test Symposium, Year: 2019
    • IETE J C Bose Memorial Award (2017)- The best engineering Oriented Work “Stability Analysis in Top-Contact and Side-Contact Graphene Nanoribbon Interconnects, Year: 2017
    • International Steering Committee Member, International Linkage Degree Programme (ILDP) Committee Japan (2018), Year: 2018
    • DST-DAAD research fellowship award, Year: 2013
    • Best Paper Award by IEEE IDICON, for the work, “Modelling of Crosstalk Delay and Noise in Single-walled Carbon Nanotube Bundle Interconnects”., Year: 2013
    • INSA-Royal Society UK fellowship Award (2006-2007), Year: 2006
    • Royal Society (UK) International Fellowship Award (2008-2009), Year: 2008
    • Science and Technology Facilities Council (STFC), UK, selected visit to Rutherford Appleton Laboratory (RAL), OXFORD, UK during March, 2009, Year: 2009
    • Best Paper Award by IEEE/ASME International Conference on Mechatronic and Embedded Systems and Applications, 2010 for the work ‘Method of Droplet Routing in Digital Microfluidic Biochip", Year: 2010
    • UGC (India Govt.) nominated visit to Hungary under Indo-Hungarian Research Exchange Program, 2006, Year: 2006
    • Best M.Tech. Thesis supervision Award to Prof. H. Rahaman by DIT, MCIT, Govt. of India under India Chip Programme during 2011-2012, Year: 2012
    • Best PhD thesis award to Dr. Debaprasad Das Supervised by Prof. Hafizur Rahaman (by IEEE Circuits & Systems Society in July 2012), Year: 2012

    Research Groups


    Anirban Bhattacharjee
    Ph. D.
    anirbanbhattacharjee330@gmail.com

    Rakesh Das
    Ph. D.
    7059070278
    rakesh.rs2017@it.iiests.ac.in / rakesh.0689@gmail.com

    Research:
    Circuits and Systems

    Annapurna Mondal
    Ph. D.
    write.to.annapurna@gmail.com

    Research:
    Circuits and Systems

    Laxmidhar Biswal
    Ph. D.
    laxmidhar.cvrce@gmail.com

    Research:
    Fault-tolerant Techniques for Synthesis of Quantum Circuits

    Anindita Chakraborty
    Ph. D.
    anindita.chakraborty.87@gmail.com

    Research:
    Memristor-based implementation of logic primitives and slicing architecture for fast computation.

    Supriyo Srimani
    Ph. D.
    supriyosriman.rs2016@vlsi.iiests.ac.in

    Research:
    Fault detection in Analog and Mixed Signal circuits using statistical and machine learning models

    Partha Sarathi Gupta
    Ph. D.
    gupta_parthasarathi@yahoo.co.in

    Research:
    Tunnel Field Effect Transistors for Optoelectronic Applications

    Bappaditya Mondal
    Ph. D.
    bappa.arya@gmail.com

    Research:
    Circuits and Systems

    Sabir Ali Mondal
    Ph. D.
    sabir.besus@gmail.com

    Research:
    Circuits and Systems

    Pampa Howladar
    Ph. D.
    p.howladar@gmail.com

    Research:
    Circuits and Systems

    Lupamudra Banerjee
    Ph. D.
    lopa.banerjee2003@gmail.com

    Research:
    Performance analysis of alternative 2-D channel materials in MOSFET

    Sudipta Bardhan
    Ph. D.
    sudipta.bardhan15@gmail.com

    Research:
    Modelling and Simulation of Graphene FET for VLSI Circuit Applications

    Malay Kule
    Ph. D.
    malay.kule@gmail.com

    Research:
    Circuits and Systems

    Subhajit Das
    Ph. D.
    sjd.subha@gmail.com

    Research:
    Interconnect modeling for future VLSI circuit design High Power on-chip circuit design

    Chandan Bandyopadhyay
    Ph. D.
    chandanb.iiest@gmail.com

    Rupam Bhattacharya
    Ph. D.
    th_rup@yahoo.co.in

    Research:
    Circuits and Systems

    Arnab Mukherjee
    Ph. D.
    arnabm.electinstru@gmail.com

    Sudip Poddar
    Ph. D.
    sudippoddar2006@gmail.com

    Research:
    Error-tolerant sample preparation with Digital microfluidic lab-on-chip

    Sarosij Adak
    Ph. D.
    sarosijadak@gmail.com

    Research:
    Analysis of GaN Based Heterostructure Nano Devices

    Kunal Sinha
    Ph. D.
    kunalsinha84@yahoo.co.in

    Research:
    Performance-Aware Stress Engineering for Nano-scaled FETs with Embedded SiGe Source and Drain

    Sandip Bhattacharya
    Ph. D.
    1983.sandip@gmail.com

    Research:
    1. Interconnect modeling for next generation on-chip integrated circuit design

    Sayan Kanungo
    Ph. D.
    sayan.kanungo@hyderabad.bits-pilani.ac.in

    Research:
    Design of Dielectrically Modulated Field Effect Transistor for Electrochemical Biosensing

    Sudip Ghosh
    Ph. D.
    sudip_etc@yahoo.co.in

    Research:
    Circuits and Systems

    Prasenjit Chanak
    Ph. D.
    prasenjit.chanak@gmail.com

    Research:
    Circuits and Systems

    Monadipan Sahoo
    Ph. D.
    9523625566 
    manodipan@iitism.ac.in

    Research:
    Circuits and Systems

    Pranab Roy
    Ph. D.
    ronmarine14@yahoo.co.in

    Research:
    Circuits and Systems

    Kamalika Dutta
    Ph. D.
    kdatta.iitkgp@gmail.com

    Research:
    Circuits and Systems

    Indrajit Banerjee
    Ph. D.
    askforindra@gmail.com

    Research:
    Circuits and Systems

    Nachiketa Das
    Ph. D.
    nachiketad@gmail.com

    Research:
    Issues of Design and Test of Field Programmable gate Array (FPGA)

    Dipak Kumar Kole
    Ph. D.
    dipak.kole@cse.jgec.ac.in

    Research:
    Circuits and Systems

    Prasun Ghosal
    Ph. D.
    prasung@gmail.com

    Research:
    Circuits and Systems

    Tuhina Samanta
    Ph. D.
    tuhina_samanta@yahoo.com

    Research:
    Circuits and Systems

    Susmit Bacchi
    Ph. D.
    profsbagchi@gmail.com

    Research:
    Circuits and Systems

    Manas Kumar Parai
    Ph. D.
    manasparai@gmail.com

    Research:
    Fault Detection in Analog Circuits

    Debaprasad Das
    Ph. D.
    dasdebaprasad@yahoo.co.in

    Research:
    Circuits and Systems

    Subhajit Chatterjee
    Ph. D.
    subhajit20@gmail.com

    Research:
    3D IC testing and verification.

    Soumyajit Poddar
    Ph. D.
    6900438944
    poddar18@gmail.com

    Research:
    Design and Evaluation of Photonic Networks-on-Chip for Many-core Architectures

    Indrajit Pan
    Ph. D.
    p.indrajit@gmail.com

    Research:
    Design and Analysis of Droplet Routing Algorithms for Digital Microfluidic Biochips

    Prasenjit Chanak
    Ph. D.
    prasenjit.cse@iitbhu.ac.in

    Research:
    Wireless Sensor Network

    Citations


    Google Scholar
    CITATION H-INDEX I-10 INDEX
    5282 30 165
    Scopus
    DOCUMENTS CITATION H-INDEX
    447 1863 17

    Created: 23 November 2019