Hafizur Rahaman received his B.E. (Electrical Engineering) from Calcutta University (B. E. College, Shibpur), M.E. (Electrical Engineering) and PhD (Computer Science and Engineering) degrees from the Jadavpur University, Calcutta, India in 1986, 1988 and 2003 respectively. Dr. Rahaman is full professor of Indian Institute of Engineering Science and Technology (IIEST), Shibpur, India. Prior to joining the IIEST Shibpur, he served as Design Engineer (System) in CMPDI (GoI R & D organization).
Dr. Rahaman visited as Post Doctoral Research Fellow under EPSARC Grant in the Design and Verification Division of Computer Science Department, Bristol University, UK during 2006-2007. During 2008-2009, Dr. Rahaman received Royal Society International Fellowship award to carry out one year advanced research in the Design and Verification Division of Computer Science Department, University of Bristol, United Kingdom. He served as visiting professor at the Computer Architecture Division, University of Germany, under DST-DAAD research fellowship award during 2013-2015.
His research interests include Logic Synthesis, design and testing of Integrated Circuits and nano-biochips, Nanoscale Technologies and Computing viz. Memristors and Reversible Quantum Circuit Synthesis etc.
He leads the VLSI design and test group, Chip-to Systems Program, GoI for fabrication of integrated circuits at IIEST, Shibpur, India,
To his credit, he has supervised 24 doctoral and forty six masters’ theses besides guiding several projects at undergraduate level. Eight more doctoral theses are now in progress.
He is also active in international collaborative research with the Bristol University (UK), University of Bremen (Germany), Duke University (USA), and Hiroshima University (Japan). He has established a strong collaboration with HiSim Laboratory, Hiroshima University since 2015. Currently he is engaged in several collaborative research projects with the different companies and research organizations including ARM, Sankalp Semiconductor.
His research has been funded by DEITY (MCIT, GoI), DST (GoI), CSIR (GoI), DIT (Gov. of WB), AICTE, UGC, Royal Society-UK, DAAD Foundation (Germany) and several industrial partners. He has contributed more than 300 research articles in archival journals and refereed conference proceedings. He has also contributed towards several book chapters in edited volumes from different publishers including CRC press, and Springer-Verlag Berlin Heidelberg etc. He published a book on emerging technology entitled “Carbon Nanotube and Graphene Nanoribbon Interconnects”, CRC Press (Taylor and Francies Group), USA, December 2014.
Dr. Rahaman is a Member of the VLSI Society of India (VSI), Senior Member of the IEEE, and ACM Sigda. He is regular reviewer of IEEE TCAD, IEEE TVLSI, IEEE TC, and ACM TODAEs. He has served/is serving as General Chair/Program Chair/Track Chair/TPC member in several conference committees including VLSI Design, VDAT, ATS, ISED, ISVLSI, ASP-DAC, ISPD, ISDCS etc.
He has initiated an IEEE International symposium on Devices, Circuits and systems (ISDCS) in collaboration with Hiroshima University, Japan under the bi-lateral cooperation between India and Japan. This symposium will be held annually in India and in Japan alternatively. This symposium will strengthen the cooperation between the two countries.
| # | Patents | Year |
|---|---|---|
| 1 | A Photonic Inter-Processor Communication Bus for Data Transfer in Homogeneous Multicore High Performance Computing Systems | 2016 |
| 2 | Crossover Biasing Technique for Quad Input Differential Amplifiers (Indian Patent No.196/KOL/2013A, Filed on 20-02-2013, Issued on 25-09-2015) | 2015 |
| 3 | A Novel Reusable Sub Volt Differential Amplifier Module for Use as a Preamplifier Output Stage (Indian Patent No. 169/KOL/2013A, 25-09-15, Filed on 20-02-2013, Issued on 25-09-2015). | 2015 |
| 4 | US Patents: Hardware accelerator for efficient convolution processing Inventors (Publication date: 2020/8/20, Application number: 16858637) | 2020 |
IEEE Computer Society
IEEE Circuits and Systems Society
IEEE Test Technology Technical Council (TTTC)
IEEE Council on Electronic Design Automation (CEDA)
International Steering Committee Member,
International Linkage Degree Programme (ILDP) Committee, Japan Since 2018
International Steering Committee Member since 2019
IEEE Asian Test Symposium under IEEE Computer Society
Institution of Engineers (India) [IEI]
Institution of Electronics and Telecommunication Engineers
VLSI Society of India (VSI)
ACM Sigda
School of VLSI Technology, IIEST Shibpur
Department of Information Technology, IIEST Shibpur
Committee for Committee for Central Facility for High End Software
Nodal Officer – Visvesvara PhD Scheme (7.5 Crore Project by Diety Micty,GOI) since 2014
Mentor Director was on Leave for USA
Co-ordinating the day to day Academic and administrative activities of IIIT Kalyani as Mentor Institute and reporting to Mentor-Director.
Setting up different Laboratories like Computer laboratory, Digital Design, Basic Electronics/Electrical Engineering, Microprocessor, Computer Architecture etc. at Indian Institute of Information Technology, Kalyani (IIIT-K) as mentor Institute.
Co-ordinating the day to day Academic and administrative activities of IIIT Kalyani as Mentor Institute and reporting to Mentor-Director
Advisory Committee on Faculty Recruitment (ACOFAR), IIEST Shibpur
School of VLSI Technology, IIEST Shibpur
Leading VLSI Activities at this Institute
Department of Information Technology, IIEST Shibpur
Department of Information Technology, IIEST Shibpur
Research:
Circuits and Systems
Research:
Circuits and Systems
Research:
Fault-tolerant Techniques for Synthesis of Quantum Circuits
Research:
Memristor-based implementation of logic primitives and slicing architecture for fast computation.
Research:
Fault detection in Analog and Mixed Signal circuits using statistical and machine learning models
Research:
Tunnel Field Effect Transistors for Optoelectronic Applications
Research:
Circuits and Systems
Research:
Circuits and Systems
Research:
Circuits and Systems
Research:
Performance analysis of alternative 2-D channel materials in MOSFET
Research:
Modelling and Simulation of Graphene FET for VLSI Circuit Applications
Research:
Circuits and Systems
Research:
Interconnect modeling for future VLSI circuit design High Power on-chip circuit design
Research:
Circuits and Systems
Research:
Error-tolerant sample preparation with Digital microfluidic lab-on-chip
Research:
Analysis of GaN Based Heterostructure Nano Devices
Research:
Performance-Aware Stress Engineering for Nano-scaled FETs with Embedded SiGe Source and Drain
Research:
1. Interconnect modeling for next generation on-chip integrated circuit design
Research:
Design of Dielectrically Modulated Field Effect Transistor for Electrochemical Biosensing
Research:
Circuits and Systems
Research:
Circuits and Systems
Research:
Circuits and Systems
Research:
Circuits and Systems
Research:
Circuits and Systems
Research:
Circuits and Systems
Research:
Issues of Design and Test of Field Programmable gate Array (FPGA)
Research:
Circuits and Systems
Research:
Circuits and Systems
Research:
Circuits and Systems
Research:
Circuits and Systems
Research:
Fault Detection in Analog Circuits
Research:
Circuits and Systems
Research:
3D IC testing and verification.
Research:
Design and Evaluation of Photonic Networks-on-Chip for Many-core Architectures
Research:
Design and Analysis of Droplet Routing Algorithms for Digital Microfluidic Biochips
Research:
Wireless Sensor Network
| Google Scholar | ||
|---|---|---|
| CITATION | H-INDEX | I-10 INDEX |
| 5282 | 30 | 165 |
| Scopus | ||
|---|---|---|
| DOCUMENTS | CITATION | H-INDEX |
| 447 | 1863 | 17 |
Created: 23 November 2019
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