Sudipta Bardhan


Designation: Assistant Professor
Degree: Ph. D.
Fellowship: Sponsorship
Enrollment No.: 362013BE2, Date: 18 Mar 2014
Registration No.: PhD/R/2015/01, Date: 13 Oct 2015Supervisor: Hafizur Rahaman

Academic Qualification

M.Tech, PhD

Research Area

Topic: Modelling and Simulation of Graphene FET for VLSI Circuit Applications

Research Area : Nanoscale Transistor


Technical Skills :

CAD Tools : Cadence,  Xilinx, Tspice, Matlab

Programming Languages : VHDL, VERILOG, VerilogA, C

Operating System : Linux, Windows.

Presently working at : Assistant Professor at Haldia Institute of Technology

Work Experience : 16 yrs.

August, 2005 to July 2009: Worked as Lecturer in Bankura Unnayani Institute of Engineering.

July. 2009 to Till Date: Working as  Assistant Professor in Haldia Institute of Technology, Haldia.


Journal :

  1. S. Bardhan, M. Sahoo, and H. Rahaman, “A Boltzmann transport equation based semiclassical drain current model for bilayer GFET including scattering effects,” IET Circuits, Devices and Systems, vol. 13, no. 4, pp. 456–464, 2019, DOI:10.1049/iet-cds.2018.5104
  2. S. Bardhan, M. Sahoo, and H. Rahaman, “Empirical drain current model of graphene FET for application as a circuit simulation tool,” IETE Journal of Research, pp. 1–13, 2019, DOI:10.1080/03772063.2019.162063
  3. S. Bardhan, M. Sahoo, and H. Rahaman, “A surface potential based model for dual gate bilayer graphene field effect transistor including the capacitive effects,” Journal of Circuits, Systems, and Computers, vol. 28, no. 14, pp. 1950241–1950261, 2019, DOI:10.1142/S0218126619502414
  4. S. Bardhan and H. Rahaman, “Modeling and Performance Analysis of Graphene Field Effect Transistor,” Asian Journal of Chemistry 25.Supplementary Issue (2013): S421


Conference :

  1. S. Bardhan, M. Sahoo, and H. Rahaman, “A verilog-a based semiclassical model for dual gated graphene field-effect transistor,” IEEE 3rd International Conference on Devices, Circuits and Systems (ICDCS), 2016, pp. 37-42.
  2. S. Bardhan, M. Sahoo, and H. Rahaman, “Analytical study of BTE based multilayer GFET model,” IEEE International Conference on Microelectronics, Computing and Communications (MicroCom), 2016, pp. 1-6.
  3. S. Bardhan, M. Sahoo, and H. Rahaman, “Analytical drain current model for graphene metal-oxide semiconductor field-effect transistor,” IEEE 2nd International Conference on Electrical Information and Communication Technology (EICT), 2015, pp. 422-427.
  4. S. Bardhan, M. Sahoo and H. Rahaman,”Analysis of Design Oriented Compact Model for ZIGZAG CNTFET,” IEEE International Conference on Electronics, Communication and Instrumentation (ICECI) 2014 Jan 16 (pp. 1-4).
  5. Sudipta Bardhan, Hafizur Rahaman, “Modeling and Performance analysis of 1D CNTFET,” National Conference on Advanced Communication Systems and  Design Techniques (NCACD) 2012.