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    Sarosij Adak

    About


    Designation: Assistant Professor
    Degree: Ph. D.
    Fellowship: UGC Fellowship
    Enrollment No.: 362014AE4, Date: 25 Sep 2014
    Registration No.: PhD/R/2015/0071, Date: 12 Aug 2015Supervisor: Hafizur Rahaman

    Academic Qualification

    • Ph.D (Engineering IIEST Shibpur)
    • M.Tech (ECE WBUT)
    • M.Sc (Electronics Vidyasagar University)

    Research Area


    Topic: Analysis of GaN Based Heterostructure Nano Devices

    Research Area : Semiconductor Device


    Skills


    Technical Skills : Semiconductor Device Design and Modelling, Numerical Device Simulation using Sentaurus TCAD and SilvacoTCAD.

    Experimental Skills : N.A.

    Presently working at :  N.A.

    Work Experience : Assistant Professor at Brainware University in the Department oF ECE [Sep2018-Dec2019]


    Publications


    Journal :

    1. Study of Linearity Performance of Graded Channel Gate stack Double Gate MOSFET with respect to high-K oxide thickness; Sanjit Kumar Swain, Satish Kumar Das, Sarosij Adak; Silicon (2019), 1-8.
    2. Impact of high–K dielectric materials on performance analysis of underlap In0.17Al0.83N/GaN DG-MOSHEMTs; Sarosij Adak, Sanjit Kumar Swain; NANO: Brief Reports and Reviews (World Scientific Publishing Company); 2019, Nano, 14(05), p.1950060.
    3. Swain, Sanjit K., Sudhansu M. Biswal, Satish K. Das, Sarosij Adak, and Biswajit Baral."Performance Comparison of InAs Based DG-MOSFET with Respect to SiO2 and Gate Stack Configuration" Nanoscience & Nanotechnology-Asia 10, no. 4 (2020): 419-424.
    4. Effect of Barrier Thickness on Linearity of Underlap AlInN/GaN DG-MOSHEMTs; Sarosij Adak, Sanjit Kumar Swain, Hemant Pardeshi, Hafizur Rahaman, Chandan Kumar Sarkar; NANO: Brief Reports and Reviews (World Scientific Publishing Company); 2017,12, (01), 1750009.
    5. High performance AlInN/AlN/GaN p-GaN Back Barrier Gate-Recessed Enhancement-Mode HEMT;Sarosij Adak, Arghyadeep Sarkar, Sanjit Swain, Hemant Pardeshi, Sudhansu Kumar Pati, Chandan Kumar Sarkar; Superlattices and Microstructure (Elsevier), 2014, 75, 347–357.
    6. Impact of gate engineering in enhancement mode n++GaN/InAlN/AlN/GaN HEMTs; Sarosij Adak, Sanjit Kumar Swain, Hafizur Rahaman, Chandan Kumar Sarkar; Superlattices and Microstructure (Elsevier), 2016,100, 306-314.
    7. Study of HfAlO/AlGaN/GaN MOS-HEMT with source field plate structure for improved breakdown voltage; Sarosij Adak, Sanjit Kumar Swain, Avtar Singh, Hemant Pardeshi, Sudhansu Kumar Pati, Chandan Kumar Sarkar; Physica E: Low-dimensional Systems and Nanostructures (Elsevier), 2014, 64, 152–157.
    8. Influence of Channel length and High-K oxide Thickness on Subthreshold DC Performance of Graded Channel and Gate stack DG-MOSFETs; Sarosij Adak, Sanjit Kumar Swain, Arka Dutta, Hafizur Rahaman, Chandan Kumar Sarkar; NANO: Brief Reports and Reviews (World Scientific Publishing Company) 2016, 11, (09), and 1650101.
    9. Analysis of flicker and thermal noise in p-channel Underlap DG FinFET; Sanjit Kumar Swain, Sarosij Adak, Sudhansu Kumar Pati, Hemant Pardeshi, Chandan Kumar Sarkar; Microelectronics Reliability (Elsevier); 2014, 54 (8), 26, 1549–1554.
    10. Effect of Channel Thickness and Doping Concentration on Sub-Threshold Performance of Graded Channel and Gate Stack DG MOSFETs; Sanjit Kumar Swain, Sarosij Adak, Bikash Sharma, Sudhansu Kumar Pati, Chandan Kumar Sarkar; Journal of Low Power Electronics (American Scientific Publishers); 2015, 11(10),1-7.
    11. Influence of channel length and high-K oxide thickness on subthreshold analog/RF performance of graded channel and gate stack DG-MOSFETs; Sanjit Kumar Swain, Arka Dutta, Sarosij Adak, Sudhansu Kumar Pati, Chandan Kumar Sarkar; Microelectronics Reliability (Elsevier); 2016, 61, 24-29.
    12. Impact of InGaN back barrier layer on performance of AIInN/AlN/GaN MOS-HEMTs; Sanjit Kumar Swain, Sarosij Adak, Sudhansu Kumar Pati, Chandan Kumar Sarkar; Superlattices and Microstructure (Elsevier), 2016, 97   (20), 258–267.

     

    Conference :

    1. Effect of AlN Spacer Layer Thickness on Device Performance of AIInN/AlN/GaN MOSHEMT; Sarosij Adak, Sanjit Kumar Swain, Hemant Pardeshi, Hafizur Rahaman, and Chandan Kumar Sarkar; International Conference on Computing Communication Control and Automation (ICCUBEA); 2015,. 902-905. IEEE.
    2. Performance analysis of gate material engineering in enhancement mode n++GaN/InAlN/AlN/GaN HEMTs; Sarosij Adak, Sanjit Kumar Swain, Godwin Raj, Hafizur Rahaman, and Chandan Kumar Sarkar; 3rd International Conference on Devices Circuits and Systems (ICDCS); 2016, 89-92. IEEE.
    3. Effect of Doping in p-GaN Gate on DC performances of AlGaN/GaN Normally-off scaled HFETs; Sarosij Adak, Sanjit Kumar Swain, Hafizur Rahaman, Chandan Kumar Sarkar; 2nd international conference on Devices for Integrated Circuit (DevIC); pp. 372-375. IEEE, 2017.
    4. Subthreshold Analog & RF Parameter extraction of GCGS DG- MOSFETs with High K material using NQS approach; Sanjit Kumar Swain, Sarosij Adak, Saradiya Parija, Chandan Kumar Sarkar; 2nd international conference on Devices for Integrated Circuit (DevIC); pp. 216-220. IEEE, 2017.
    5. Comparison of linearity Performance of InAs based  DG-MOSFETs with Gate Stack,SiO2 and HfO2; Sanjit Kumar Swain, Sarosij Adak, Sudhansu Mohan Biswal, Biswajit Baral, Saradiya Parija, In 2018 IEEE Electron Devices Kolkata Conference (EDKCON), pp. 242-246. IEEE, 2018.
    6. Study of Linearity Performances of Junction less Triple Material Cylindrical Surrounding Gate MOSFET; Pradipta Kumar Jena, Sanjit Kumar Swain, Omprakash Acharya, Sarosij Adak, In 2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC), vol. 1, pp. 1-4. IEEE, 2018.
    7. Effect of AlGaN Back Barrier on InAlN/AlN/GaN E-Mode HEMT; Sarosij Adak, Nisarga Chand, Sanjit Kumar Swain, Angsuman Sarkar, 3rd international conference on Devices for Integrated Circuit (2019 IEEE DevIC), pp. 156-160. IEEE, 2019.
    8. Effect of High-K Spacer on the Performance of Non-Uniformly doped DG-MOSFET; Sanjit Kumar Swain, Satish Kumar Das, Sudhansu Mohan Biswal, Sarosij Adak, Umakanta Nanda, Asmit Amlan Sahoo, 3rd international conference on Devices for Integrated Circuit (2019 IEEE DevIC), pp. 510-514. IEEE, 2019.
    9. Impact of high K layer material on Analog/RF performance of forward and reversed   Graded channel Gate Stack DG-MOSFETs; Sanjit Kumar Swain, Sarosij Adak, Arka Dutta, Godwin Raj, and Chandan Kumar Sarkar; 3rd International Conference on Devices, Circuits and Systems (ICDCS); 2016, pp. 98-102. IEEE, 2016.