| # | List of Publication by Dr. Surajit Kumar Roy |
|---|---|
| 1 | Rakesh Mondal, Surajit Kumar Roy and Chandan Gir, Solar Power Forecasting Using Domain Knowledge, Energy, 2024 |
| 2 | Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri, Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs, 94, 1-9, Integration, VLSI Journal, 2024 |
| 3 | Dilip Kumar Maity, Surajit Kumar Roy and Chandan Giri, Cluster-Aware Allocation of Spare TSVs for Enhanced Reliability in 3D ICs, Microelectronics Reliability, 2023 |
| 4 | Sourav Ghosh, Surajit Kumar Roy, Chandan Giri, Fault Detection and Diagnosis of DMFB Using Concurrent Electrodes Actuation, 39(1), 89-102, J. Electron. Test., 2023 |
| 5 | Tapobrata Dhar, Ranit Das, Chandan Giri, Surajit Kumar Roy, Threshold Analysis Using Probabilistic Xgboost Classifier for Hardware Trojan Detection, 39(4), 447-463, J. Electron. Test, 2023 |
| 6 | A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs, Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri, 18(4), ACM Journal on Emerging Technologies in Computing System, 2022 |
| 7 | Subhajit Chatterjee, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman, Frequency-scaled thermal-aware test scheduling for 3D ICs using machine learning based temperature estimation, Microelectronics Journal, 2022 |
| 8 | Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri, TSV-Cluster Defect Tolerance Using Tree-Based Redundancy for Yield Improvement of 3-D ICs, 40(8), 1500-1510, IEEE Transaction on Comput. Aided Des. Integr. Circuits System, 2021 |
| 9 | Dilip Kumar Maity, Surajit Kumar Roy and Chandan Giri, Identification of Random/Clustered TSV Defects in 3D IC during Pre-bond Testing, Accepted for publication in Journal of Electronic Testing:Theory and Applications (JETTA), Springer, 2019 |
| 10 | Surajit Kumar Roy, Chandan Giri and HafizurRahaman, Optimization of Test Wrapper for TSV Based 3D SOCs, 32(5), 511-529, journal of Electronic Testing, 2016 |
| 11 | Surajit Kumar Roy, Chandan Giri and Hafizur Rahaman, Optimization of Test Architecture in 3D Stacked ICs for Partial Stack/Complete Stack using Hard SOCs, 9(5), 268-274, Journal of IEEE Computer and Digital Techniques, 2015 |
Created: 23 November 2019