| # | List of Publication by Dr. Sudip Ghosh |
|---|---|
| 1 | Utsob Dhara, Subhrajyoti Choudhury, Sudip Ghosh and Hafizur Rahaman, ASIC Design and Implementation of Fast 2D Gaussian Filter Chip Using Approximate Computing, DOI : 10.1007/s00034-025-03318-z, Springer CSSP, 2025 |
| 2 | Rupam Sardar, Sudip Ghosh, Bimal Datta, Designing Half-Adder with CMOS Technology using Artificial Neural Network with Verilog Implementation, Volume: 08 Issue: 03, International Journal of Scientific Research in Engineering and Management (IJSREM), 2024 |
| 3 | Rupam Sardar, Sudip Ghosh, Bimal Datta, Full Adder Circuit Design with CMOS Technology Implementing with Artificial Neural Network with Verilog HDL Code for Output, Volume: 08 Issue: 03, International Journal of Scientific Research in Engineering and Management (IJSREM), 2024 |
| 4 | Rupam Sardar, Sudip Ghosh and Bimal Datta,, Prediction of Humidity using Multi Linear Perceptron and Support Vector Machine North Twenty-four Parganas, West Bengal, Volume: 08 Issue: 03, International Journal of Scientific Research in Engineering and Management (IJSREM), 2024 |
| 5 | Sudip Ghosh, Yuvam Bhateja, Joshua Roy Palathinkal, Hafizur Rahaman, Hardware Design with Real-Time Implementation for Security of Medical Images and EPMR, vol 41, pp. 867–891, Springer Circuits Systems and Signal Processing (CSSP), 2021 |
| 6 | Subhajit Das , Sudip Ghosh, Nachiketa Das , Santi P. Maity , Hafizur Rahaman, Reshmi Maity and Niladri Maity, Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach, Volume 37, Issue 4, pp 1575–1593, Springer Circuits Systems and Signal Processing (CSSP), 2018 |
| 7 | Sambaran Hazra, Sudip Ghosh, Sayandip De and Hafizur Rahaman, FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time, vol 14, pp. 193-221, Springer journal of Real-Time Image Processing (RTIP), 2017 |
| 8 | Sudip Ghosh,Arijit Biswas, Santi Prasad Maity and Hafizur Rahaman, Field Programmable Gate Array and System-on-Chip Based Implementation of Discrete Fast Walsh-Hadamard Transform Domain Image Watermarking Architecture For Real-Time Applications, Vol. 11, No. 3, pp. 375-386, Journal of Low Power Electronics (JOLPE), 2015 |
| 9 | Sudip Ghosh, Somsubhra Talapatra, Navonil Chatterjee, Santi P Maity and Hafizur Rahaman, FPGA based Implementation of Embedding and Decoding Architecture for Binary Watermark by Spread Spectrum Scheme in Spatial Domain, Vol. 2, No. 4, pp. 01-08, Bonfring International Journal of Advances in Image Processing, 2012 |
Created: 23 November 2019