| # | List of Publication by Prof. Surajeet Ghosh |
|---|---|
| 1 | A. Sarkar and S. Ghosh, Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pair-Wise Sequence Alignment, Early Access, pp. 1–14, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 |
| 2 | S. Ghosh, CB-ED-RPL: Coordinator-Based Energy-Efficient Dynamic RPL for IoT Networks, Wireless Personal Communications, Springer Nature, 2023 |
| 3 | S. S. Ray, D. Adak and S. Ghosh, Worst Case O(N) Comparison-Free Hardware Sorting Engine, vol. 41, no. 10, pp. 3332-3345, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (Early Access 2021), 2022 |
| 4 | S. S. Ray, S. Ghosh and B. Sardar, Memory Efficient Hash-Based Longest Prefix Matching Architecture with Zero False +ve and Nearly Zero False -ve Rate for IP Processing, Vol. 71, No. 6, pp. 1261 - 1275, IEEE Transactions on Computers, (Early Access 2021), 2022 |
| 5 | S. Ray and S. Ghosh, k-Degree Parallel Comparison-free Hardware Sorter for Complete Sorting, pp. 1-12, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Early Access, 2022 |
| 6 | S. Ghosh and S. S. Ray, O(N) Memory-Free Hardware Architecture for Burrows-Wheeler Transform, pp. 1–14, IEEE Transactions on Computers, Early Access, 2022 |
| 7 | A. Sarkar, S. Ghosh and S. Saha Ray, A Hardware-Based Memory-Efficient Solution for Pair-Wise Compact Sequence Alignment, 1-12, IETE Journal of Research, Taylor & Francis, 2021 |
| 8 | A. Sarkar, S. Banerjee and S. Ghosh, An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological Sequence Alignment, Vol. 28, No. 12, pp. 2598 – 2611, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020 |
| 9 | S. K. Ray and S. Ghosh, Binarily Gapped Binary Insertion Sorting Technique, 64(3), 337-346, Institution of Electronics and Telecommunication Engineers (IETE) Journal of Research, 2018 |
| 10 | S. Saha Ray, K. Das and S. Ghosh, A RAM-Based MAC Table with Two-Tier Security at Layer 2, 62(4), 435-445, IETE Journal of Research, 2016 |
| 11 | S. S. Ray, S. Ghosh and B. Sardar, SRAM Based Novel Hardware Architecture for Longest Prefix Matching for IP Route Lookup, 32(3), 359 – 371, Photonic Network Communications – Springer, 2016 |
| 12 | S. Ghosh, S. Saha Ray, 4th Generation Progrqammable Logic Computing: A Road Map, 24(6), 439 - 452, IETE Technical Review, 2007 |
Created: 23 November 2019