| # | List of Publication by Prof. Surajeet Ghosh |
|---|---|
| 1 | S. Ghosh and A. Chand, CB-RPL: Coordinator-Based RPL for Energy Efficient Routing Mechanism, 231-236, 2022 IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS), Gandhinagar, December, 2022 |
| 2 | S. Ghosh, S. Dasgupta, and S. Saha Ray, A Comparison-free Hardware Sorting Engine, 586-591, 2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Miami, Florida, 2019 |
| 3 | A. Sarkar, K. Ray, D. Chowdhury, K. Sahu, S. Kundu and S. Ghosh, Time and Space Efficient Optimal Pairwise Sequence Alignment using GPU, 2019 IEEE Region 10 Conference (TENCON), Kochi, Kerala, 2019 |
| 4 | S. Saha Ray, S. Singh, C. Sengupta, S. Ghosh and B. Sardar, A Fine-grained Integrated IP Lookup Engine for Multigigabit IP Processing, 2018 IEEE International Conference on Advanced Networks and Telecommunications Systems (ANTS), Indore, India, 16-19 December 2018., 2018 |
| 5 | A. Sarkar and S. Ghosh, A Coarse-Grained Pipeline Architecture for Sequence Alignment, 2018 15th IEEE India Council International Conference (INDICON), Coimbatore, India, December 16 – 18, 2018., 2018 |
| 6 | D. Sharma, A. Gupta, A. K. Layek and S. Ghosh, Movable Wireless Access Point for IoT-Based Home Automation, 2018 15th IEEE India Council International Conference (INDICON), Coimbatore, India, December 16 – 18., 2018 |
| 7 | S. Ghosh and A. Sarkar, An FPGA-Based Processor for Compact Sequence Alignment, IEEE International conference on Electronics, Communication and Aerospace Technology (IEEE ICECA 2018), 2018 |
| 8 | S. Ghosh, S. Kesharwani, V. Mishra and S. S. Ray, Hybrid trie based approach for longest prefix matching in IP packet processing, 1532-1537, TENCON 2017 - IEEE Region 10 Conference, 2017 |
| 9 | S. S. Ray, N. Srivastava and S. Ghosh, A Hardware-Based High-Throughput DNA Sequence Alignment Scheme, 1 -6, India Conference (INDICON), 2016 Annual IEEE, Bengaluru, 2016, 2016 |
| 10 | S. Saha Ray, A. Banerjee, A. Datta and S. Ghosh, A Memory Efficient DNA Sequence Alignment Technique Using Pointing Matrix, 3559 – 3562, TENCON 2016 - 2016 IEEE Region 10 Conference, Singapore, 2016 |
| 11 | S. Ghosh and M. Baliyan, A Hash Based Architecture of Longest Prefix Matching for Fast IP Processing, 228 – 231, TENCON 2016 - 2016 IEEE Region 10 Conference, Singapore, 2016 |
| 12 | S. S. Ray, S. Ghosh and B. Sardar, SRAM based longest prefix matching approach for multigigabit IP processing, 1-6, 2015 IEEE International Conference on Advanced Networks and Telecommuncations Systems (ANTS), Kolkata, 2015, 2015 |
| 13 | S. Ghosh, S. Mandal and S. Saha Ray, A scalable high-throughput pipeline architecture for DNA sequence alignment, 1-6, TENCON 2015 - 2015 IEEE Region 10 Conference, Macao, 2015, 2015 |
| 14 | S. S. Ray, S. Ghosh, R. Prasad, Low-cost hierarchical memory-based pipelined architecture for DNA sequence matching, 1-6, India Conference (INDICON), 2014 Annual IEEE, 2014 |
| 15 | S. S. Ray, A. Bhattacharya, S. Ghosh, A fast range matching architecture with unit storage expansion ratio and high memory utilization using SBiCAM for packet classification, 1-6, India Conference (INDICON), 2014 Annual IEEE, 2014 |
| 16 | S. S. Ray, A. Chatterjee, S. Ghosh, A novel approach for prefix minimization using Ternary Trie (PMTT) for packet classification, 1-6, TENCON 2014 - 2014 IEEE Region 10 Conference, 2014 |
| 17 | S. S. Ray, A. Chatterjee, S. Ghosh, A Hierarchical High-throughput and Low Power Architecture for Longest Prefix Matching for Packet Forwarding, 628-631, Proc. of IEEE International Conference on Computational Intelligence and Computing Research, (Available in IEEE Xplore Digital Library), Madurai 26th-28th Dec. 2013. Print ISBN: 978-1-4799-1594-1, 2013 |
| 18 | S. Ghosh, S. S. Ray, S. Mandal, High Through-put Scalable Query Processing Architecture using STCAM, 650-653, Proc. of IEEE International Conference on Computational Intelligence and Computing Research, (Available in IEEE Xplore Digital Library), Madurai 26th-28th Dec. 2013, Print ISBN: 978-1-4799-1594-1, 2013 |
| 19 | S. Saha Ray, S. Ghosh, Smart Ternary Content Addressable Memory (STCAM) Architecture, 434 – 438, Ieee International Conference on Advanced Communication Control and Computing Technologies (Icaccct) (Available in IEEE Xplore Digital Library), Ramanathapuram, 2012 |
| 20 | S. Ghosh, J. Ghosh, S. Saha Ray, Architecture of Configurable K-way C-access Interleaved Memory, nternational Conference on Process Automation Control and Computing (ICPACC) (Available in IEEE Xplore Digital Library), Coimbatore, 20-22 July 2011. Print ISBN: 978-1-61284-765-8, 2011 |
| 21 | S. K. Ray, S. Ghosh, Low-Cost dictionary machine using RAM -Based CAM, 559-566, International Conference on Advanced Computing (ICAC 09), Tiruchirappalli, Aug. 6-8, 2009 |
| 22 | S. Ghosh, S. Saha Ray, Register Size Programmable Autoconfigured Register Size for RISC Processors, Proceedings of International Conference on Embedded Systems and VLSI Design (ICVLSI), Chennai, Feb 14-16, 2008, 2008 |
Created: 23 November 2019